Delta ASD-B2-1521-F, Руководство пользователя

Страница: 232 / 345

ASDA-B2 Chapter 7 Parameters
Revision May, 2018
7-71
Setting Value Speed Estimation Bandwidth (Hz)
1E 125
1F 100
P2-50 CCLR Pulse Clear Mode
Address: 0264H
0265H
Operation
Interface:
Panel/Software Communication
Related Section: N/A
Default: 00
Control
Mode:
PT
Unit: N/A
Range: 0 ~ 11
Data Size: 16-bit
Format: Hexadecimal
Settings:
For digital input setting, please refer to Table 7.1.
When set digital input (DI) as CCLR, the function of pulse clear is
effective.
 Triggering Method Settings:
0: CCLR is triggered by rising-edge
1: CCLR is triggered by level
 Function Selection Settings:
0: When this DI is on, the accumulative position error will be
cleared to 0.
1: When this DI is on, the feedback PUU will be cleared to 0.
P2-51 Reserved
Address: 0266H
0267H
P2-52 Reserved
Address: 0268H
0269H