Agilent Technologies J-BERT N4903, Руководство пользователя

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The exact time delay through a test setup can vary. The delay function
allows you to compensate for this by adjusting the frequency reference
for the data outputs. This varies the phase relationship of the data and
clock outputs (causes the data pulse to have a certain time delay after
the clock pulse). The higher the delay, the greater the time difference
between the clock signal and the data signal.
Crossover is the voltage level where the overlapped rising and falling
edges of the logic levels intersect. This adjustment varies the widths of
the logic highs and lows.
The following figure shows examples of crossover at 50 %, 80 %, and
20 %:
Understanding how the Serial BERT Uses Logic Families and
Terminations
The clock and data inputs of your device have load impedances (or
terminations). Clock and data terminations refer to the voltage levels at
the end of these loads. These voltage levels are related to the logic family
of your device. Your device should usually only receive signals that are
compatible with its termination voltage and logic family.
When you change a logic family for the data or clock outputs, the
termination voltage normally associated with the logic family is
automatically selected. This is assumed to be the termination of your
device, and will be used to determine the actual output voltage levels of
the pattern generator.
3
Setting up the Pattern Generator
74 Agilent J-BERT N4903 High-Performance Serial BERT
Delay
Crossover