Agilent Technologies J-BERT N4903, Руководство пользователя

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The following figure illustrates how the duration of the Gate In signal
can influence the bit count time (the time where bits are actually
counted).
Data Input
Gate Input
CDR Settling Time
Synchronization Time
Bit Count Time
Burst
Gate Active
Valid after Gate
Begin Margin End Margin
Gate
Passive
Gate Active is the interval in which the Gate In signal is active.
The Bit Count Time is the part of the burst from which the bits can
actually be counted. The remainder of the burst is covered by the
Begin
Margin
and
End Margin
.
The CDR Settling Time is the time that the error detector requires in
CDR mode to get the clock from the data stream.
The Synchronization Time is the time the error detector requires to
synchronize to the pattern. This time depends on the pattern type
(PRBS or memory-based).
The Valid after Gate indicates the minimum length of data that has to
arrive at Data In after the Gate In signal is deactivated.
There is no requirement how long a signal should be available at Data
In before gating starts (the data should simply be stable). A pause is
however required after the gating to allow the error detector to evaluate
the results. This time is known as
Gate Passive .
The following is a summary of the values of these parameters for the
Serial BERT:
Table 15
Parameter Values
Bit Count Time Min.: 1536 bits
Max: 4 Gbits
The optimal length is dependent on the
BER threshold.
Setting up the Error Detector
4
Agilent J-BERT N4903 High-Performance Serial BERT 147
Interval between Bursts