Schweitzer Engineering Laboratories SEL-311L, Instruction Manual, Page: 184 / 734

5-8 Trip and Target Logic Date Code 20010625
SEL-311L Instruction Manual
Unlatch Trip
Once Relay Word bit TRIP is asserted to logical 1, it remains asserted at logical 1 until all the
following conditions come true:
v
Minimum Trip Duration Timer stops timing (logic output of the TDURD timer goes to
logical 0)
v
Output of OR-1 gate in Figure 5.4 deasserts to logical 0
v
One of the following occurs:
SEL
OGIC
control equation setting ULTR asserts to logical 1,
The front-panel TARGET RESET button is pressed,
Or the TAR R (Target Reset) command is executed via the serial port.
The front-panel TARGET RESET button and the TAR R (Target Reset) serial port command are
primarily used during testing. Use these to force the TRIP Relay Word bit to logical 0 if test
conditions are such that setting ULTR does not assert to logical 1 to automatically deassert the
TRIP Relay Word bit.
Other Applications for the Target Reset Function
Note that the combination of the TARGET RESET Pushbutton and the TAR R (Target Reset)
serial port command is also available as Relay Word bit TRGTR. See Figure 5.19 and
accompanying text for applications for Relay Word bit TRGTR.
Factory Settings Example (Using Setting TR)
In this example the “communications-assisted” and “switch-onto-fault” trip logic at the top of
Figure 5.4 are not used. The SEL
OGIC
control equation trip setting TR is now the only input into
OR-1 gate and flows into the “seal-in and unlatch” logic for Relay Word bit TRIP.
The factory settings for the trip logic SEL
OGIC
control equation settings are:
TR = M1P + Z1G + M2PT + Z2GT + 51GT + 51QT + OC (trip conditions)
ULTR = !(50L + 51G) (unlatch trip conditions)
The factory setting for the Minimum Trip Duration Timer setting is:
TDURD = 9.000 cycles
See the settings sheets in Section 9: Setting the Relay for setting ranges.