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Date Code 20011112
Line Current Differential, Distance, Out-of-Step, Overcurrent,
3-27
Voltage, Synchronism Check, and Frequency Elements
SEL-311L Instruction Manual
B8
7L2
R8
7L2
87
LOP2
87
L2
P
(S
et
ting)
87L2P*
(S
et
ting)
1/
2*
0
0
7
+
–
–
+
87
L2
1
0
H
1
0
1/
8
0
H
|3I
L2
+ 3I
R2
|
∑
Alpha Plane
Set
tings
87LANG
, 8
7LR
3I2, 3I1
Calc
• C
TR
÷
CTRMAX
÷
CTRMAX
• C
TR_X
3I2, 3I1
Calc
to T
apped
Load Elements
3I2L
3I2X
Align
Ia, Ib
, Ic
Lo
ca
l
Ia, Ib
, Ic
Channel X
Primary Curr
ents
to METER
Enable
87L2E
+
–
–
+
+
–
+
–
50R2
50L2
5% Inom
3I
1L
• 0
.0
5
3I
1R
• 0
.0
5
All 3 phase
curr
ents fr
om an
y
terminal
≥
3 Inom
M311L0
79
a
Sum
* Timer incr
eases t
o 1.5 cy
cles and
set
ting 8
7L2P triples when:
1. B8
7L2 asserts
.
2. 3PO or Negativ
e Disturbanc
e Det
ect
or
(NDD
) assert, and f
or 3 cy
cles af
ter 3PO
and NDD deassert. NDD asserts on f
alling
I1 t
o desensitiz
e sequenc
e elements
during br
eak
er opening on e
xt
ernal
faults
.
3. F
or 1.5 cy
cle
s af
ter an
y r
emot
e phase
curr
ent e
xc
eeds local set
ting 50LP while
the associat
ed r
emot
e 3PO bit is assert
ed
or within 3 cyles af
te
r the r
emot
e 3PO bit
deasserts
.
H: Timer
s mark
ed with "H" ar
e h
ys
te
re
sis
count
er
s.
CTRMAX is the
maximum o
f
set
tings C
TR
,
CTR_X, and C
TR_Y
.
3I
2R
3I
2R
3I
2L
3I
2L
Rela
y
Wo
rd
Bits
Rela
y
Wo
rd
Bit
Rela
y
Wo
rd
Bit
Rela
y
Wo
rd
Bit
Rela
y
Wo
rd
Bit
Rela
y
Wo
rd
Bit
A
A
Figure 3.18: Negative-Sequence Differential Element 87L2 Processing for Channel X.
Channel Y Processing Similar.
Summary of Contents for SEL-311L
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