Renesas H8/38024 Series, Hardware Manual

Page: 589 / 661

Rev. 6.00, 08/04, page 559 of 628
TCSRF—Timer Control/Status Register F H'B7 Timer F
Bit
Initial value
Read/Write
Note:
*
Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
7
OVFH
0
R/(W)
*
6
CMFH
0
R/(W)
*
5
OVIEH
0
R/W
0
CCLRL
0
R/W
2
CMFL
0
R/(W)
*
1
OVIEL
0
R/W
4
CCLRH
0
R/W
Compare Match Flag H
0 Clearing condition:
After reading CMFH = 1, cleared by writing 0 to CMFH
1 Setting condition:
Set when the TCFH value matches the OCRFH value
Timer Overflow Flag H
0
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1 Setting condition:
Set when TCFH overflows from H'FF to H'00
Compare Match Flag L
0 Clearing condition:
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting condition:
Set when the TCFL value matches the OCRFL value
Timer Overflow Flag L
0 Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting condition:
Set when TCFL overflows from H'FF to H'00
Counter Clear H
0 16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
1 16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Timer Overflow Interrupt Enable H
0
TCFH overflow interrupt request is disabled
1 TCFH overflow interrupt request is enabled
Timer Overflow Interrupt Enable L
Counter Clear L
0 TCFL overflow interrupt request is disabled
1 TCFL overflow interrupt request is enabled
0 TCFL clearing by compare match is disabled
1 TCFL clearing by compare match is enabled
3
OVFL
0
R/(W)
*