Renesas H8/38024 Series, Hardware Manual

Page: 339 / 661

Rev. 6.00, 08/04, page 309 of 628
Event Counter Control/Status Register (ECCSR)
OVH CUEL CRCH CRCL OVL

CH2 CUEH
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W
*
R/W R/W R/W R/W
*
R/W R/W R/W
Bit
Note:
*
Bits 7 and 6 can only be written with 0, for flag clearing.
Initial Value
Read/Write
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Bit 7—Counter Overflow H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by
reading it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a
status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
Description
0 ECH has not overflowed (initial value)
Clearing condition:
After reading OVH = 1, cleared by writing 0 to OVH
1 ECH has overflowed
Setting condition:
Set when ECH overflows from H’FF to H’00
Bit 6—Counter Overflow L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by
reading it when set to 1, then writing 0.