Renesas H8/38024 Series, Hardware Manual

Page: 320 / 661

Rev. 6.00, 08/04, page 290 of 628
9.6 Watchdog Timer
9.6.1 Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024F-
ZTAT Group and for the H8/38124 Group are different.
Features
Features of the watchdog timer are given below.
•
Incremented by internal clock source (
φ
/8192 or
φ
w/32) on the H8/38024, H8/38024S, and
H8/38024F-ZTAT Group.
•
On the H8/38124 Group, 10 internal clocks (
φ
/64,
φ
/128,
φ
/256,
φ
/512,
φ
/1024,
φ
/2048,
φ
/4096,
φ
/8192,
φ
w/32, or watchdog on-chip oscillator) are available for selection for use by
the counter.
•
A reset signal is generated when the counter overflows. The overflow period can be set from 1
to 256 times the selected clock (from approximately 4 ms to 1,000 ms when
φ
= 2.00 MHz).
•
Use of module standby mode enables this module to be placed in standby mode independently
when not used. See section 5.9, Module Standby Mode, for details.