Renesas H8/38024 Series, Hardware Manual

Page: 166 / 661

Rev. 6.00, 08/04, page 136 of 628
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Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the
DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1
bits STS2 to STS0 has elapsed.
5.8.2 Direct Transition Times
1. Time for direct transition from active (high-speed) mode to active (medium-speed) mode
A direct transition from active (high-speed) mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in active (high-speed) mode while bits SSBY and LSON are both
cleared to 0 in SYSCR1, and bits MSON and DTON are both set to 1 in SYSCR2. The time from
execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition
time) is given by equation (1) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } • (tcyc before transition) + (number of interrupt
exception handling execution states) • (tcyc after transition)
.................................. (1)
Example: Direct transition time = (2 + 1) • 2tosc + 14 • 16tosc = 230tosc (when
φ
/8 is selected as
the CPU operating clock)
[Legend]
tosc: OSC clock cycle time
tcyc: System clock (
φ
) cycle time