Rev. 6.00, 08/04, page 149 of 628
Figure 6.5 shows a PROM write/verify timing diagram.
Write
Input data
Output data
Verify
Address
Data
V
PP
V
PP
t
AS
t
AH
t
DS
t
DH
t
DF
t
OE
t
OES
t
PW
t
OPW
*
t
VPS
t
VCS
t
CES
V
CC
V
CC
CE
PGM
OE
V
CC
+1
V
CC
Note:
*
t
OPW
is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6.5 PROM Write/Verify Timing
Summary of Contents for H8/38024 Series
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Page 661: ...H8 38024 H8 38024S H8 38024F ZTAT H8 38124 Group Hardware Manual...
