Renesas H8/38024 Series, Hardware Manual

Page: 117 / 661

Rev. 6.00, 08/04, page 87 of 628
Wakeup Edge Select Register (WEGR)
Bit
Initial value
Read/Write
7
WKEGS7
0
R/W
6
WKEGS6
0
R/W
5
WKEGS5
0
R/W
4
WKEGS4
0
R/W
3
WKEGS3
0
R/W
0
WKEGS0
0
R/W
2
WKEGS2
0
R/W
1
WKEGS1
0
R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins
WKP
n.
WEGR is initialized to H'00 by a reset.
Bit n—
WKP WKP WKP WKP
n Edge Select (WKEGSn)
Bit n selects
WKP
n pin input sensing.
Bit n
WKEGSn
Description
0
WKP
n pin falling edge detected (initial value)
1
WKP
n pin rising edge detected
(n = 7 to 0)
3.3.3 External Interrupts
There are 13 external interrupts: WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0, and IRQAEC.
Interrupts WKP
7
to WKP
0
Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins
WKP
7
to
WKP
0
. When these pins are designated as pins
WKP
7
to
WKP
0
in port mode register 5 and a
rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR.
Vector number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the
same vector number, so the interrupt-handling routine must discriminate the interrupt source.