Renesas H8/38024 Series, Hardware Manual

Page: 482 / 661

Rev. 6.00, 08/04, page 452 of 628
Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2).
2. The figure in parentheses applies when an external clock is used.
3. After powering on, hold V
CC
at 2.2 V to 5.5 V until the chip's oscillation settling time has
elapsed.
Table 16.4 Serial Interface (SCI3) Timing
V
CC
= 1.8 V to 5.5 V, AV
CC
= 1.8 V to 5.5 V, V
SS
= AV
SS
= 0.0 V, T
a
= –20°C to +75°C (regular
specifications), T
a
= –40°C to +85°C (wide-range specifications), T
a
= +75°C (Die) (including
subactive mode) unless otherwise indicated.
Values
Item Symbol Min Typ Max Unit Test Conditions
Reference
Figure
Asynchronous t
scyc
4 — — t
cyc
or Figure 16.4 Input clock
cycle
Synchronous 6 — — t
subcyc
Input clock pulse width t
SCKW
0.4 — 0.6 t
scyc
Figure 16.4
t
TXD
— — 1 t
cyc
or V
CC
= 4.0 V to 5.5 V Figure 16.5 Transmit data delay time
(synchronous)
— — 1 t
subcyc
Except the above
t
RXS
200.0 — — ns V
CC
= 4.0 V to 5.5 V Figure 16.5 Receive data setup time
(synchronous)
400.0 — — Except the above Figure 16.5
t
RXH
200.0 — — ns V
CC
= 4.0 V to 5.5 V Figure 16.5 Receive data hold time
(synchronous)
400.0 — — Except the above Figure 16.5