Renesas H8/38024 Series, Hardware Manual

Page: 327 / 661

Rev. 6.00, 08/04, page 297 of 628
Bit 3
CKS3 Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0
Description
1 0 0 0 Internal clock:
φ
/64 count
1 Internal clock:
φ
/128 count
1 0 Internal clock:
φ
/256 count
1 Internal clock:
φ
/512 count
1 0 0 Internal clock:
φ
/1024 count
1 Internal clock:
φ
/2048 count
1 0 Internal clock:
φ
/4096 count
1 Internal clock:
φ
/8192 count (initial value)
0 X X X Watchdog on-chip oscillator
Note: X: Don't care
Clock Stop Register 2 (CKSTPR2)
LVDCKSTD
*
WDCKSTP PW1CKSTP LDCKSTP
 
PW2CKSTP AECKSTP
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
R/W R/W R/W R/W
 
R/W R/W
Bit
Initial value
Read/Write
Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group.
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the watchdog timer is described here. For details of the other
bits, see the sections on the relevant modules.
Bit 2—Watchdog Timer Module Standby Mode Control (WDCKSTP)
Bit 2 controls setting and clearing of module standby mode for the watchdog timer.
WDCKSTP Description
0 Watchdog timer is set to module standby mode
1 Watchdog timer module standby mode is cleared (initial value)
Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W
(TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer
operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog
function and will not enter module standby mode. When the watchdog function ends and
WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the
watchdog timer will enter module standby mode.