Renesas H8/38024 Series, Hardware Manual

Page: 306 / 661

Rev. 6.00, 08/04, page 276 of 628
Bit 5—Timer Overflow Interrupt Enable (OVIE)
Bit 5 selects enabling or disabling of interrupt generation when TCG overflows.
Bit 5
OVIE
Description
0 TCG overflow interrupt request is disabled (initial value)
1 TCG overflow interrupt request is enabled
Bit 4—Input Capture Interrupt Edge Select (IIEGS)
Bit 4 selects the input capture input signal edge that generates an interrupt request.
Bit 4
IIEGS
Description
0 Interrupt generated on rising edge of input capture input signal (initial value)
1 Interrupt generated on falling edge of input capture input signal
Bits 3 and 2—Counter Clear 1 and 0 (CCLR1, CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
CCLR1 Bit 2
CCLR0
Description
0 0 TCG clearing is disabled (initial value)
0 1 TCG cleared by falling edge of input capture input signal
1 0 TCG cleared by rising edge of input capture input signal
1 1 TCG cleared by both edges of input capture input signal
Bits 1 and 0—Clock Select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Bit 1
CKS1 Bit 0
CKS0
Description
0 0 Internal clock: counting on
φ
/64 (initial value)
0 1 Internal clock: counting on
φ
/32
1 0 Internal clock: counting on
φ
/2
1 1 Internal clock: counting on
φ
w/4