Rev. 6.00, 08/04, page 90 of 628
•
The I bit of CCR is set to 1, masking further interrupts.
•
The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
Summary of Contents for H8/38024 Series
Page 18: ...Rev 6 00 08 04 page xviii of xxx...
Page 30: ...Rev 6 00 08 04 page xxx of xxx...
Page 130: ...Rev 6 00 08 04 page 100 of 628...
Page 216: ...Rev 6 00 08 04 page 186 of 628...
Page 416: ...Rev 6 00 08 04 page 386 of 628...
Page 432: ...Rev 6 00 08 04 page 402 of 628...
Page 468: ...Rev 6 00 08 04 page 438 of 628...
Page 661: ...H8 38024 H8 38024S H8 38024F ZTAT H8 38124 Group Hardware Manual...
