Renesas H8/38024 Series Hardware Manual Download | Manualshive

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Rev. 6.00, 08/04, page 193 of 628

Bit 2—Watchdog Timer Source Clock (WDCKS)

This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024,
H8/38024S, and H8/38024F-ZTAT Group and for the H8/38124 Group are different.

•

H8/38024, H8/38024S, H8/38024F-ZTAT Group

Bit 2
WDCKS

Description

0

Selects

φ

/8192

(initial value)

1

Selects

φ

W

/32

•

H8/38124 Group

Bit 2
WDCKS

Description

0

Selects clock based on timer mode register W (TMW) setting

*

(initial value)

1

Selects

φ

W

/32

Note:

*

See section 9.6, Watchdog Timer, for details.

Bit 1—TMIG Noise Canceller Select (NCS)

This bit selects controls the noise cancellation circuit of the input capture input signal (TMIG).

Bit 1
NCS

Description

0

No noise cancellation circuit

(initial value)

1

Noise cancellation circuit

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221
222
223
224
225
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Summary of Contents for H8/38024 Series

Page 1: ...Bit Single Chip Microcomputer H8 Family H8 300L Super Low Power Series Rev 6 00 REJ09B0042 0600O The revision list can be viewed directly by clicking the title page The revision list summarizes the l...

Page 2: ...total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from...

Page 3: ...ization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on th...

Page 4: ...e functional description of each module differs according to the module However the generic style includes the following items i Feature ii Input Output Pin iii Register Description iv Operation v Usa...

Page 5: ...rocomputer allowing the implementation of a sophisticated control system Versions are available with types of internal ROM flash memory F ZTAT 1 and PROM ZTAT 2 This makes it possible to design applic...

Page 6: ...Output only 6 6 6 6 6 6 6 I O 51 51 51 51 51 50 50 Timers Clock timer A 1 1 1 1 1 1 1 Reload timer C 1 1 1 1 1 1 1 Compare timer F 1 1 1 1 1 1 1 Capture timer G 1 1 1 1 1 1 1 AEC 1 1 1 1 1 1 1 WDT 1...

Page 7: ...control functions peripheral functions and electrical characteristics in that order To understanding CPU functions Refer to the separate H8 300L Series Programming Manual Explanatory Note Bit sequence...

Page 8: ...must be mounted on the user board 3 The address range H 7000 to H 7FFF is used by the on chip emulator and is unavailable to the user 4 The address range H F780 to H FB7F must not be accessed under a...

Page 9: ...is changed from 1 to 0 while pin 6 is low and WEGR bit WKEGS6 1 IWPF5 When PMR5 bit WKP5 is changed from 0 to 1 while pin 5 is low and WEGR bit WKEGS5 0 When PMR5 bit WKP5 is changed from 1 to 0 while...

Page 10: ...by timer A timer C timer F timer G SCI3 the A D converter the LCD controller watchdog timer and the 10 bit PWM The divider ratio can be set separately for each on chip peripheral function 4 5 1 Defin...

Page 11: ...e amended 9 2 1 Overview 238 Features Description deleted Use of module standby mode enables this module to be placed in standby mode independently when not used 9 4 2 Register Descriptions 258 Timer...

Page 12: ...nformation on retaining voltage 14 2 1 Low Voltage Detection Control Register LVDCR Table 14 3 LVDCR Settings and Function Register Selections 428 Note added Note Setting values marked with an asteris...

Page 13: ...8 DC Characteristics 462 Table amended Values Item Symbol Applicable Pi ns Min Typ Max Unit Test Condit ion Notes IOL Output pins except port 9 0 5 mA Allowable output low current per pin P90 to P92...

Page 14: ...ol Applicable Pins Min Typ Max Unit Test Condition Notes VOH VCC 1 0 V VCC 4 0 V to 5 5 V IOH 1 0 mA Output high voltage VCC 0 5 VCC 4 0 V to 5 5 V IOH 0 5 mA P13 P14 P17 P30 to P37 P40 to P42 P50 to...

Page 15: ...M VCC 2 0 V 6 RAM data retaining voltage current consump tion 0 5 VCC 2 7 V Ta 25 C 32 kHz crystal resonator not used 2 3 4 Reference value 0 05 VCC 2 7 V Ta 25 C SUBSTP subclock oscillator control re...

Page 16: ...ng production lots When designing systems make sure to give due consideration to the SPEL range Please see the Web site for this product for actual performance data 16 8 5 LCD Characteristics Table 16...

Page 17: ...38123H 38123 H 80 pin QFP FP 80A Mask ROM versions Regular specifications HD64338123W 38123 80 pin TQFP TFP 80C HD64338123HW 38123 H 80 pin QFP FP 80A Wide range specifications HD64338123WW 38123 80 p...

Page 18: ...Rev 6 00 08 04 page xviii of xxx...

Page 19: ...Registers 30 2 3 2 Memory Data Formats 31 2 4 Addressing Modes 32 2 4 1 Addressing Modes 32 2 4 2 Effective Address Calculation 34 2 5 Instruction Set 38 2 5 1 Data Transfer Instructions 40 2 5 2 Arit...

Page 20: ...Response Time 94 3 4 Application Notes 95 3 4 1 Notes on Stack Area Use 95 3 4 2 Notes on Rewriting Port Mode Registers 96 3 4 3 Method for Clearing Interrupt Request Flags 98 Section 4 Clock Pulse G...

Page 21: ...eep Mode 132 5 5 2 Clearing Subsleep Mode 132 5 6 Subactive Mode 133 5 6 1 Transition to Subactive Mode 133 5 6 2 Clearing Subactive Mode 133 5 6 3 Operating Frequency in Subactive Mode 133 5 7 Active...

Page 22: ...6 7 3 Notes on On Board Programming 165 6 8 Flash Memory Programming Erasing 165 6 8 1 Program Program Verify 165 6 8 2 Erase Erase Verify 169 6 8 3 Interrupt Handling when Programming Erasing Flash...

Page 23: ...1 Overview 207 8 5 2 Register Configuration and Description 207 8 5 3 Pin Functions 210 8 5 4 Pin States 211 8 5 5 MOS Input Pull Up 211 8 6 Port 6 212 8 6 1 Overview 212 8 6 2 Register Configuration...

Page 24: ...nagement of the Un Use Terminal 236 Section 9 Timers 237 9 1 Overview 237 9 2 Timer A 238 9 2 1 Overview 238 9 2 2 Register Descriptions 240 9 2 3 Timer Operation 243 9 2 4 Timer A Operation States 24...

Page 25: ...Register RSR 323 10 2 2 Receive Data Register RDR 323 10 2 3 Transmit Shift Register TSR 324 10 2 4 Transmit Data Register TDR 324 10 2 5 Serial Mode Register SMR 325 10 2 6 Serial Control Register 3...

Page 26: ...n 394 12 3 1 A D Conversion Operation 394 12 3 2 Start of A D Conversion by External Trigger Input 394 12 3 3 A D Converter Operation Modes 395 12 4 Interrupts 395 12 5 Typical Use 395 12 6 A D Conver...

Page 27: ...ply Step Down Circuit 439 15 2 When Not Using Internal Power Supply Step Down Circuit 440 Section 16 Electrical Characteristics 441 16 1 H8 38024 ZTAT Version and Mask ROM Version Absolute Maximum Rat...

Page 28: ...8 Power On Reset Circuit Characteristics 509 16 8 9 Watchdog Timer Characteristics 510 16 9 Operation Timing 510 16 10 Output Load Circuit 513 16 11 Resonator Equivalent Circuit 513 16 12 Usage Note 5...

Page 29: ...04 page xxix of xxx Appendix E List of Product Codes 616 Appendix F Package Dimensions 619 Appendix G Specifications of Chip Form 623 Appendix H Form of Bonding Pads 625 Appendix I Specifications of C...

Page 30: ...Rev 6 00 08 04 page xxx of xxx...

Page 31: ...oup H8 38024S Group and H8 38124 Group are the H8 38024 H8 38024S and H8 38124 with on chip 32 Kbyte ROM and 1 Kbyte RAM the H8 38023 H8 38023S and H8 38123 with on chip 24 Kbyte ROM and 1 Kbyte RAM t...

Page 32: ...operating at 8 MHz 2 8 s operating at 5 MHz Can run on 32 768 kHz or 38 4 kHz subclock 32 768 kHz only for H8 38124 Group Instruction set compatible with H8 300 CPU Instruction length of 2 bytes or 4...

Page 33: ...n modes Seven power down modes Sleep high speed mode Sleep medium speed mode Standby mode Watch mode Subsleep mode Subactive mode Active medium speed mode Memory Large on chip memory H8 38024 H8 38024...

Page 34: ...unted both rising and falling edge detection possible Timer C 8 bit timer Count up down timer with selection of seven internal clock signals or event input from external pin Auto reloading Timer F 16...

Page 35: ...ns Conversion time 31 or 62 per channel LCD controller driver LCD controller driver equipped with a maximum of 32 segment pins and four common pins Choice of four duty cycles static 1 2 1 3 or 1 4 Seg...

Page 36: ...0C Die 12K 512 HD64338020 FP 80A FP 80B TFP 80C Die 8K 512 HD64338024S FP 80A TFP 80C TLP 85V Die 32K 1K HD64338023S FP 80A TFP 80C TLP 85V Die 24K 1K HD64338022S FP 80A TFP 80C TLP 85V Die 16K 1K HD6...

Page 37: ...COM1 P77 SEG24 P76 SEG23 P75 SEG22 P74 SEG21 P73 SEG20 P72 SEG19 P71 SEG18 P70 SEG17 P87 SEG32 P86 SEG31 P85 SEG30 P84 SEG29 P83 SEG28 P82 SEG27 P81 SEG26 P80 SEG25 P60 SEG9 P61 SEG10 P62 SEG11 P63 S...

Page 38: ...EG10 P62 SEG11 P63 SEG12 P64 SEG13 P65 SEG14 P66 SEG15 P67 SEG16 P40 SCK32 P41 RXD32 P42 TXD32 P43 IRQ0 OSC1 OSC2 x1 x2 P13 TMIG P14 IRQ4 ADTRG P17 IRQ3 TMIF P30 UD P31 TMOFL P32 TMOFH P33 P34 P35 P36...

Page 39: ...55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P30 UD P31 TMOFL P32 TMOFH P33 P34...

Page 40: ...2 V SS AV SS OSC 2 OSC 1 TEST RES P5 0 WKP 0 SEG 1 P5 1 WKP 1 SEG 2 P5 2 WKP 2 SEG 3 P5 3 WKP 3 SEG 4 P5 4 WKP 4 SEG 5 P5 5 WKP 5 SEG 6 P5 6 WKP 6 SEG 7 P5 7 WKP 7 SEG 8 P83 SEG28 P82 SEG27 P81 SEG26...

Page 41: ...ES P5 0 WKP 0 SEG 1 P5 1 WKP 1 SEG 2 P5 2 WKP 2 SEG 3 P5 3 WKP 3 SEG 4 P5 4 WKP 4 SEG 5 P5 5 WKP 5 SEG 6 P5 6 WKP 6 SEG 7 P5 7 WKP 7 SEG 8 P6 0 SEG 9 P6 1 SEG 10 P81 SEG26 P80 SEG25 P77 SEG24 P76 SEG2...

Page 42: ...C8 C9 C10 D1 D2 D3 D4 D8 D9 D10 E1 E2 E3 E8 E9 E10 F1 F2 F3 F8 F9 F10 G1 G2 G3 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 TLP 85V Top view...

Page 43: ...7 9 11 13 15 17 19 21 2 4 6 8 10 12 14 16 18 20 22 23 80 78 76 74 72 70 68 66 64 62 25 27 29 31 33 35 37 39 41 24 26 28 30 32 34 36 38 40 Chip size 3 99 mm 3 99 mm Voltage level on the back of the ch...

Page 44: ...780 1872 63 P31 TMOFL 1621 1872 23 P61 SEG10 1621 1872 64 P32 TMOFH 1084 1872 24 P62 SEG11 1037 1872 65 P33 948 1872 25 P63 SEG12 896 1872 66 P34 810 1872 26 P64 SEG13 765 1872 67 P35 673 1872 27 P65...

Page 45: ...67 65 80 78 76 74 72 70 68 66 64 1 3 5 7 9 11 13 15 17 19 21 23 2 4 6 8 10 12 14 16 18 20 22 24 26 25 28 30 32 34 36 38 40 27 29 31 33 35 37 39 41 Y X 0 0 Type code Chip size 3 84 mm 4 24 mm Voltage l...

Page 46: ...UD 1802 1904 23 P60 SEG9 1802 1904 64 P31 TMOFL 1686 1999 24 P61 SEG10 1686 1999 65 P32 TMOFH 1222 1999 25 P62 SEG11 1198 1999 66 P33 1077 1999 26 P63 SEG12 1057 1999 67 P34 932 1999 27 P64 SEG13 916...

Page 47: ...34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 0 Y X Chip size 2 91 mm 2 91 mm Voltage level on the back of the c...

Page 48: ...RQAEC 1338 1147 21 P60 SEG9 1121 1338 61 P30 UD 1131 1338 22 P61 SEG10 927 1338 62 P31 TMOFL 936 1338 23 P62 SEG11 805 1338 63 P32 TMOFH 831 1338 24 P63 SEG12 703 1338 64 P33 735 1338 25 P64 SEG13 593...

Page 49: ...er supply 0 V AVCC 1 3 B1 1 2 1 Input Analog power supply This is the power supply pin for the A D converter When the A D converter is not used connect this pin to the system power supply AVSS 8 VSS 1...

Page 50: ...ut Test pin This pin is reserved and cannot be used It should be connected to VSS Interrupt pins IRQ0 IRQ1 IRQ3 IRQ4 72 76 5 3 74 78 7 5 C5 B3 D1 B2 73 77 5 3 74 78 6 4 72 76 5 3 Input IRQ interrupt r...

Page 51: ...The counter operates as a down counter when this pin is high and as an up counter when low TMIF 5 7 D1 5 6 5 Input Timer F event input This is an event input pin for input to the timer F counter TMOFL...

Page 52: ...he user P43 72 74 C5 73 74 72 Input Port 4 bit 3 This is a 1 bit input port P42 to P40 71 to 69 73 to 71 B6 B5 C6 72 to 70 73 to 71 71 to 69 I O Port 4 bits 2 to 0 This is a 3 bit I O port Input or ou...

Page 53: ...o PA0 45 to 48 47 to 50 G10 G8 G9 F10 46 to 49 47 to 50 45 to 48 I O Port A This is a 4 bit I O port Input or output can be designated for each bit by means of port control register A PCRA PB7 to PB0...

Page 54: ...put These are the LCD segment output pins NC NC A1 A10 D4 K2 K10 NC pin Vref 57 Input LVD reference voltage input This is the LVD reference voltage input pin Low voltage detect circuit LVD 4 extD 73 I...

Page 55: ...iply and divide instructions Powerful bit manipulation instructions Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post increment o...

Page 56: ...ture of the H8 300L CPU There are two groups of registers the general registers and control registers 7 0 7 0 15 0 7 6 5 4 3 2 1 0 I U H U N Z V C PC R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4...

Page 57: ...e stack pointer SP used implicitly by hardware in exception processing and subroutine calls When it functions as the stack pointer as indicated in figure 2 2 SP R7 points to the top of the stack Lower...

Page 58: ...and is cleared to 0 otherwise The H flag is used implicitly by the DAA and DAS instructions When the ADD W SUB W or CMP W instruction is executed the H flag is set to 1 if there is a carry or borrow a...

Page 59: ...instruction executed after a reset 2 3 Data Formats The H8 300L CPU can process 1 bit data 4 bit BCD data 8 bit byte data and 16 bit word data Bit manipulation instructions operate on 1 bit data spec...

Page 60: ...nH 7 6 5 4 3 2 1 0 Don t care 7 0 1 bit data RnL MSB LSB Don t care 7 0 Byte data RnH Byte data RnL Word data Rn 4 bit BCD data RnH 4 bit BCD data RnL Legend RnH RnL MSB LSB Upper byte of general regi...

Page 61: ...codes Data Format 7 6 5 4 3 2 1 0 Address Data Type 7 0 Address n MSB LSB MSB LSB Upper 8 bits Lower 8 bits MSB LSB CCR CCR MSB LSB MSB LSB Address n Even address Odd address Even address Odd address...

Page 62: ...indirect aa 8 Register Direct Rn The register field of the instruction specifies an 8 or 16 bit general register containing the operand Only the MOV W ADD W SUB W CMP W ADDS SUBS MULXU 8 bits 8 bits...

Page 63: ...and bit manipulation instructions can use 8 bit absolute addresses The MOV B MOV W JMP and JSR instructions can use 16 bit absolute addresses For an 8 bit absolute address the upper 8 bits are assumed...

Page 64: ...ee section 2 3 2 Memory Data Formats for further information 2 4 2 Effective Address Calculation Table 2 2 shows how effective addresses are calculated in each of the addressing modes Arithmetic and l...

Page 65: ...dicated by rm 0 15 Register indirect with displacement d 16 Rn op rm rn 8 7 3 4 0 15 op rm 7 6 3 4 0 15 disp op rm 7 6 3 4 0 15 Register indirect with post increment Rn op rm 7 6 3 4 0 15 Register ind...

Page 66: ...ulation Method Effective Address EA 5 Absolute address aa 8 Operand is 1 or 2 byte immediate data aa 16 op 8 7 0 15 op 0 15 IMM op disp 7 0 15 Program counter relative d 8 PC 6 7 0 15 PC contents 0 15...

Page 67: ...n Format No Effective Address Calculation Method Effective Address EA 8 Memory indirect aa 8 op 8 7 0 15 Memory contents 16 bits 0 15 abs H 00 8 7 0 15 Legend rm rn op disp IMM abs Register field Oper...

Page 68: ...OTXL ROTXR 8 Bit manipulation BSET BCLR BNOT BTST BAND BIAND BOR BIOR BXOR BIXOR BLD BILD BST BIST 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control RTE SLEEP LDC STC ANDC ORC XORC NOP 8 Block data tra...

Page 69: ...r N N negative flag of CCR Z Z zero flag of CCR V V overflow flag of CCR C C carry flag of CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplicat...

Page 70: ...n aa 16 xx 16 Rn and Rn addressing modes are available for word data The aa 8 addressing mode is available for byte data only The R7 and R7 modes require word operands Do not specify byte size for the...

Page 71: ...p rm rn Rm Rn or Rn Rm 15 0 8 7 op rn abs aa 8 Rn 15 0 8 7 op rn aa 16 Rn abs 15 0 8 7 op rn IMM xx 8 Rn 15 0 8 7 op rn xx 16 Rn IMM 15 0 8 7 op rn PUSH POP Legend op rm rn disp abs IMM Operation fiel...

Page 72: ...1 Rd Increments or decrements a general register by 1 ADDS SUBS W Rd 1 Rd Rd 2 Rd Adds or subtracts 1 or 2 to or from a general register DAA DAS B Rd decimal adjust Rd Decimal adjusts adjusts to 4 bit...

Page 73: ...R operation on a general register and another general register or immediate data NOT B Rd Rd Obtains the one s complement logical complement of general register contents Notes Size Operand size B Byte...

Page 74: ...end op rm rn IMM Operation field Register field Immediate data 15 0 8 7 op rn ADDS SUBS INC DEC DAA DAS NEG NOT 15 0 8 7 op rn MULXU DIVXU rm 15 0 8 7 rn IMM ADD ADDX SUBX CMP XX 8 op 15 0 8 7 op rn A...

Page 75: ...three bits of a general register BTST B bit No of EAd Z Tests a specified bit in a general register or memory and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate d...

Page 76: ...gister or memory to the C flag BILD B bit No of EAd C Copies the inverse of a specified bit in a general register or memory to the C flag The bit number is specified by 3 bit immediate data BST B C bi...

Page 77: ...0 IMM 15 0 8 7 op 0 Operand Bit No register indirect Rn register direct Rm rn 0 0 0 0 0 0 0 rm op 15 0 8 7 op Operand Bit No absolute aa 8 immediate xx 3 abs 0 0 0 0 IMM op op 15 0 8 7 op Operand Bit...

Page 78: ...ata 15 0 8 7 op IMM rn Operand Bit No register direct Rn immediate xx 3 BIAND BIOR BIXOR BILD BIST 15 0 8 7 op 0 Operand Bit No register indirect Rn immediate xx 3 rn 0 0 0 0 0 0 0 IMM op 15 0 8 7 op...

Page 79: ...on BRA BT Always true Always BRN BF Never false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow c...

Page 80: ...ield Displacement Absolute address 15 0 8 7 op cc disp Bcc 15 0 8 7 op rm 0 JMP Rm 0 0 0 15 0 8 7 op JMP aa 16 abs 15 0 8 7 op abs JMP aa 8 15 0 8 7 op disp BSR 15 0 8 7 op rm 0 JSR Rm 0 0 0 15 0 8 7...

Page 81: ...n 5 Power Down Modes for details LDC B Rs CCR IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified ge...

Page 82: ...hows its object code format Table 2 11 Block Data Transfer Instruction Instruction Size Function EEPMOV If R4L 0 then repeat R5 R6 R4L 1 R4L until R4L 0 else next Block transfer instruction Transfers...

Page 83: ...Rev 6 00 08 04 page 53 of 628 Legend op Operation field 15 0 8 7 op op Figure 2 10 Block Data Transfer Instruction Code...

Page 84: ...e cycle differs depending on whether access is to on chip memory or to on chip peripheral modules 2 6 1 Access to On Chip Memory RAM ROM Access to on chip memory takes place in two states The data bus...

Page 85: ...accessing word data two instructions must be used Figures 2 12 and 2 13 show the on chip peripheral module access cycle Two state access to on chip peripheral modules T1 state Bus cycle T2 state or S...

Page 86: ...modules T1 state Bus cycle Internal address bus Internal read signal Internal data bus read access Internal write signal Read data Address Internal data bus write access T2 state T3 state Write data o...

Page 87: ...e high speed mode Active medium speed mode Subactive mode Sleep high speed mode Standby mode Watch mode Subsleep mode Low power modes The CPU executes successive program instructions at high speed syn...

Page 88: ...e system clock in active mode high speed and medium speed and with the subclock in subactive mode See section 5 Power Down Modes for details on these modes 2 7 3 Program Halt State In the program halt...

Page 89: ...128 bytes Workarea for reprogramming flash memory 1 Kbyte 2 Internal I O register Not used Firmware for on chip emulator 1 H F780 Not used Not used LCD RAM 16 bytes H 0000 H 0029 H 002A H 7FFF H F740...

Page 90: ...5FFF H F740 H F74F H FB80 H FF7F H FF80 H FFFF Interrupt vector area On chip ROM 24 Kbytes 24576 bytes 1024 bytes On chip RAM Internal I O registers 128 bytes Not used Not used LCD RAM 16 bytes Figur...

Page 91: ...3FFF H F740 H F74F H FB80 H FF7F H FF80 H FFFF Interrupt vector area On chip ROM 16 Kbytes 16384 bytes 1024 bytes On chip RAM Internal I O registers 128 bytes Not used Not used LCD RAM 16 bytes Figur...

Page 92: ...H 2FFF H F740 H F74F H FD80 H FF7F H FF80 H FFFF Interrupt vector area On chip ROM 12 Kbytes 12288 bytes 512 bytes On chip RAM Internal I O registers 128 bytes Not used Not used LCD RAM 16 bytes Figur...

Page 93: ...H 1FFF H F740 H F74F H FD80 H FF7F H FF80 H FFFF Interrupt vector area On chip ROM 8 Kbytes 8192 bytes 512 bytes On chip RAM Internal I O registers 128 bytes Not used Not used LCD RAM 16 bytes Figure...

Page 94: ...I O Registers Internal data transfer to or from on chip modules other than the ROM and RAM areas makes use of an 8 bit data width If word access is attempted to these areas the following results will...

Page 95: ...he address is H 5FFF on the H8 38022 H8 38122 and H8 38022S 16 Kbytes and the address is H 3FFF on the H8 38021 H8 38121 and H8 38021S 12 Kbytes and the address is H 2FFF on the H8 38020 H8 38120 and...

Page 96: ...ister and timer counter Figure 2 18 shows an example in which two timer registers share the same address When a bit manipulation instruction accesses the timer load register and timer counter of a rel...

Page 97: ...put Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR3 0 0 1 1 1 1 1 1 PDR3 0 1 0 0 0 0 0 1 D Explanation of how...

Page 98: ...el Low level Low level PCR3 0 0 1 1 1 1 1 1 PDR3 1 0 0 0 0 0 0 0 RAM0 1 0 0 0 0 0 0 0 B BSET instruction executed BSET 0 RAM0 The BSET instruction is executed designating the PDR3 work area RAM0 C Aft...

Page 99: ...3 The BCLR instruction is executed designating PCR3 C After executing BCLR P37 P36 P35 P34 P33 P32 P31 P30 Input output Output Output Output Output Output Output Output Input Pin state Low level High...

Page 100: ...RAM0 0 0 1 1 1 1 1 1 B BCLR instruction executed BCLR 0 RAM0 The BCLR instruction is executed designating the PCR3 work area RAM0 C After executing BCLR MOV B RAM0 R0L The work area RAM0 value is writ...

Page 101: ...Registers with Write Only Bits Register Name Abbreviation Address Port control register 1 PCR1 H FFE4 Port control register 3 PCR3 H FFE6 Port control register 4 PCR4 H FFE7 Port control register 5 PC...

Page 102: ...e number of bytes specified by R4L from the address specified by R5 to the address specified by R6 R6 R6 R4L R5 R5 R4L When setting R4L and R6 make sure that the final destination address R6 R4L does...

Page 103: ...Overview A reset is the highest priority exception The internal state of the CPU and the registers of the on chip peripheral modules are initialized 3 2 2 Reset Sequence As soon as the RES pin goes lo...

Page 104: ...initial instruction prefetch 1 Reset exception handling vector address H 0000 2 Program start address 3 First instruction of program 2 3 2 1 Reset cleared Figure 3 1 Reset Sequence 3 2 3 Interrupt Imm...

Page 105: ...n more than one interrupt is requested the interrupt with the highest priority is processed The interrupts have the following features Internal and external interrupts can be masked by the I bit in CC...

Page 106: ...counter overflow 12 H 0018 to H 0019 Timer C Timer C overflow or underflow 13 H 001A to H 001B Timer FL Timer FL compare match Timer FL overflow 14 H 001C to H 001D Timer FH Timer FH compare match Tim...

Page 107: ...bled only for writing of 0 to clear a flag IRQ Edge Select Register IEGR Bit Initial value Read Write 7 1 6 1 5 1 4 IEG4 0 R W 3 IEG3 0 R W 0 IEG0 0 R W 2 W 1 IEG1 0 R W IEGR is an 8 bit read write re...

Page 108: ...n and TMIC pin Bit 1 IEG1 Description 0 Falling edge of IRQ1 and TMIC pin input is detected initial value 1 Rising edge of IRQ1 and TMIC pin input is detected Bit 0 IRQ0 Edge Select IEG0 Bit 0 selects...

Page 109: ...requests Bit 5 IENWP Description 0 Disables WKP7 to WKP0 interrupt requests initial value 1 Enables WKP7 to WKP0 interrupt requests Bits 4 and 3 IRQ4 and IRQ3 Interrupt Enable IEN4 and IEN3 Bits 4 an...

Page 110: ...0 R W 1 IENTC 0 R W IENR2 is an 8 bit read write register that enables or disables interrupt requests Bit 7 Direct Transfer Interrupt Enable IENDT Bit 7 enables or disables direct transfer interrupt...

Page 111: ...Bit 3 IENTFH Description 0 Disables timer FH interrupt requests initial value 1 Enables timer FH interrupt requests Bit 2 Timer FL Interrupt Enable IENTFL Bit 2 enables or disables timer FL compare m...

Page 112: ...0 R W 2 IRREC2 0 R W 1 IRRI1 0 R W Note Only a write of 0 for flag clearing is possible IRR1 is an 8 bit read write register in which a corresponding flag is set to 1 when a timer A IRQAEC IRQ4 IRQ3...

Page 113: ...Interrupt Request Flag IRREC2 Bit 2 IRREC2 Description 0 Clearing conditions initial value When IRREC2 1 it is cleared by writing 0 1 Setting conditions When pin IRQAEC is designated for interrupt inp...

Page 114: ...are not cleared automatically when an interrupt is accepted It is necessary to write 0 to clear each flag Bit 7 Direct Transfer Interrupt Request Flag IRRDT Bit 7 IRRDT Description 0 Clearing conditio...

Page 115: ...n IRRTFH 1 it is cleared by writing 0 1 Setting conditions When TCFH and OCRFH match in 8 bit timer mode or when TCF TCFL TCFH and OCRF OCRFL OCRFH match in 16 bit timer mode Bit 2 Timer FL Interrupt...

Page 116: ...te Only a write of 0 for flag clearing is possible IWPR is an 8 bit read write register containing wakeup interrupt request flags When one of pins WKP7 to WKP0 is designated for wakeup input and a ris...

Page 117: ...errupts WKP7 to WKP0 IRQ4 IRQ3 IRQ1 IRQ0 and IRQAEC Interrupts WKP7 to WKP0 Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to WKP0 When these pins are design...

Page 118: ...signal to pin IRQAEC and IECPWM output of PWM for AEC When the IRQAEC input pin is to be used as an external interrupt set ECPWME in AEGSR to 0 This interrupt is detected by rising edge falling edge...

Page 119: ...ontroller When the interrupt controller receives an interrupt request it sets the interrupt request flag From among the interrupts with interrupt request flags set to 1 the interrupt controller select...

Page 120: ...or address is executed Notes 1 When disabling interrupts by clearing bits in an interrupt enable register or when clearing bits in an interrupt request register always do so while interrupts are maske...

Page 121: ...ution state No Yes Yes No Legend PC CCR I Program counter Condition code register I bit of CCR IEN0 1 No Yes IENDT 1 No Yes IRRDT 1 No Yes Branch to interrupt handling routine IRRI0 1 No Yes IEN1 1 No...

Page 122: ...rogram counter PC Lower 8 bits of program counter PC Condition code register Stack pointer Notes CCR CCR PCH PCL 1 2 PC shows the address of the first instruction to be executed upon return from the i...

Page 123: ...ted Address is saved as PC contents becoming return address 2 4 Instruction code not executed 3 Instruction prefetch address Instruction is not executed 5 SP 2 6 SP 4 7 CCR 8 Vector address 9 Starting...

Page 124: ...st flag is set until the first instruction of the interrupt handler is executed Table 3 4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction 1 to 13 15 to 27...

Page 125: ...shown in figure 3 6 PC PC R1L PC SP SP SP H FEFC H FEFD H FEFF H L L MOV B R1L R7 SP set to H FEFF Stack accessed beyond SP BSR instruction Contents of PC are lost H Legend PCH PCL R1L SP Upper byte...

Page 126: ...e 3 5 shows the conditions under which interrupt request flags are set to 1 in this way Table 3 5 Conditions under which Interrupt Request Flag is Set to 1 Interrupt Request Flags Set to 1 Conditions...

Page 127: ...o 0 while pin WKP3 is low and WEGR bit WKEGS3 1 IWPF2 When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low and WEGR bit WKEGS2 0 When PMR5 bit WKP2 is changed from 1 to 0 while pin WKP2 is...

Page 128: ...ear interrupt request flag to 0 CCR I bit 0 Figure 3 7 Port Mode Register or AEGSR Setting and Interrupt Request Flag Clearing Procedure 3 4 3 Method for Clearing Interrupt Request Flags Use the recom...

Page 129: ...01 R1L Here IRRI0 1 MOV B R1L IRR1 8 IRRI0 is cleared to 0 In the above example it is assumed that an IRQ0 interrupt is generated while the AND B instruction is executing The IRQ0 interrupt is disable...

Page 130: ...Rev 6 00 08 04 page 100 of 628...

Page 131: ...es an on chip oscillator 4 1 1 Block Diagram Figure 4 1 shows a block diagram of the clock pulse generators of the H8 38024 H8 38024S and H8 38024F ZTAT Group Figure 4 2 shows a block diagram of the c...

Page 132: ...lock and Subclock The basic clock signals that drive the CPU and on chip peripheral modules are and SUB Four of the clock signals have names is the system clock SUB is the subclock OSC is the oscillat...

Page 133: ...ntrol SUBSTP Bit 7 controls whether the subclock oscillator operates or not It can be set to 1 only in the active mode high speed medium speed Setting bit 7 to 1 in the subactive mode will cause the L...

Page 134: ...shown in figure 4 2 the H8 38124 Group supports selection between a system clock oscillator and an on chip oscillator See section 4 2 On Chip Oscillator Selection Method for information on selecting t...

Page 135: ...with the resonator manufacturer Figure 4 3 2 Typical Connection to Crystal Oscillator H8 38024S H8 38124 Group Figure 4 3 shows the equivalent circuit of a crystal oscillator An oscillator having the...

Page 136: ...SC2 Rf C1 C2 CSTCC2M00G53 B0 CSTCC2M00G56 B0 CSTLS10M0G53 B0 CSTLS10M0G56 B0 CSTLS16M0X53 B0 15 pF 20 47 pF 20 15 pF 20 47 pF 20 15 pF 20 C1 C2 Recommendation value Notes Circuit constants should be d...

Page 137: ...he crystal or ceramic oscillator and floating capacitance when designing the board When using the oscillator consult with the crystal or ceramic oscillator manufacturer to determine the circuit parame...

Page 138: ...1 and OSC2 if the on chip oscillator is selected In this case pin OSC1 should be fixed at VCC or GND Note The system clock oscillator must be selected in order to program or erase flash memory as part...

Page 139: ...4 2 Note that only operation at 32 768 kHz is guaranteed on the H8 38124 Group X X C1 C2 1 2 C C 15 pF typ 1 2 Frequency 38 4 kHz 32 768 kHz Crystal oscillator Seiko Instrument Inc Nihon Denpa Kogyo P...

Page 140: ...38124 Group X1 External clock input X2 Open Figure 4 11 Pin Connection when Inputting External Clock Frequency Subclock w Duty 45 to 55 Method for Disabling Subclock Oscillator H8 38124 Group Only The...

Page 141: ...lse generator stops Prescaler S also stops and is initialized to H 0000 The CPU cannot read or write prescaler S The output from prescaler S is shared by timer A timer C timer F timer G SCI3 the A D c...

Page 142: ...Vss P17 X1 X2 Vss OSC2 OSC1 TEST Figure 4 12 Example of Crystal and Ceramic Oscillator Element Arrangement Figure 4 13 1 shows an example measuring circuit with the negative resistance suggested by th...

Page 143: ...Circuit Modification Suggestions 4 5 1 Definition of Oscillation Stabilization Wait Time Figure 4 14 shows the oscillation waveform OSC2 system clock and microcomputer operating mode when a transition...

Page 144: ...abilization time Operating mode Standby mode watch mode or subactive mode Wait time Oscillation stabilization wait time Active high speed mode or active medium speed mode Interrupt accepted Figure 4 1...

Page 145: ...tallation circuit before deciding on the oscillation stabilization wait time In particular since the oscillation stabilization time is affected by installation circuit constants stray capacitance and...

Page 146: ...o drop to ground potential before powering on once again 4 6 Notes on H8 38124 Group When using the on chip emulator system clock precision is necessary for programming or erasing the flash memory How...

Page 147: ...halts On chip peripheral functions are operable on the system clock Sleep medium speed mode The CPU halts On chip peripheral functions operate at a frequency of 1 128 1 64 1 32 or 1 16 of the system...

Page 148: ...to 5 8 Notes 1 2 Mode Transition Conditions 1 a b c d e f g h i j LSON MSON SSBY DTON 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 Don t care Mode Transition Conditions 2 1 In...

Page 149: ...d 11 Timer F Timer G Functions Retained 9 Functions Retained 9 Functions Retained 9 Retained SCI3 Reset Functions Retained 3 Functions Retained 3 Reset PWM Retained Retained Retained Retained A D conv...

Page 150: ...r 1 SYSCR1 R W H 07 H FFF0 System control register 2 SYSCR2 R W H F0 H FFF1 System Control Register 1 SYSCR1 Bit Initial value Read Write 7 SSBY 0 R W 6 STS2 0 R W 5 STS1 0 R W 4 STS0 0 R W 3 LSON 0 R...

Page 151: ...Wait time 16 384 states 0 1 0 Wait time 1 024 states 0 1 1 Wait time 2 048 states 1 0 0 Wait time 4 096 states 1 0 1 Wait time 2 states External clock input mode 1 1 0 Wait time 8 states 1 1 1 Wait t...

Page 152: ...Bits 1 and 0 Active Medium Speed Mode Clock Select MA1 MA0 Bits 1 and 0 choose osc 128 osc 64 osc 32 or osc 16 as the operating clock in active medium speed mode and sleep medium speed mode MA1 and M...

Page 153: ...on a combination of other control bits Bit 3 DTON Description 0 When a SLEEP instruction is executed in active mode initial value a transition is made to standby mode watch mode or sleep mode When a...

Page 154: ...P instruction is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0 the MSON and DTON bits in SYSCR2 are cleared to 0 In sleep mode CPU operation is halted but the on chip peripheral fun...

Page 155: ...speed mode to active medium speed mode Sleep mode is not cleared if the I bit of the condition code register CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register T...

Page 156: ...rrupt IRQ1 or IRQ0 WKP7 to WKP0 or by input at the RES pin Clearing by interrupt When an interrupt is requested the system clock pulse generator starts After the time set in bits STS2 to STS0 in SYSCR...

Page 157: ...y and Stabilization Time H8 38024 H8 38024S H8 38024F ZTAT Group Unit ms STS2 STS1 STS0 Wait Time 5 MHz 2 MHz 0 0 0 8 192 states 1 638 4 1 1 16 384 states 3 277 8 2 1 0 1 024 states 0 205 0 512 1 2 04...

Page 158: ...or active medium speed mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1 and bit TMA3 is cleared to 0 in TMA a transition is made to standby mode At the same time pins go to the...

Page 159: ...signals cannot be captured because internal clock stops The case of falling edge capture is illustrated in figure 5 3 As shown in the case marked Capture not possible when an external input signal fal...

Page 160: ...l Active high speed medium speed mode or subactive mode Active high speed medium speed mode or subactive mode Standby mode or watch mode Wait for oscillation to settle tcyc tsubcyc tcyc tsubcyc tcyc t...

Page 161: ...n is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2 If both LSON and MSON are cleared to 0 transition is to active high speed mode if LSON 0 and MSON 1 transition is to active mediu...

Page 162: ...he transition 5 5 2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt timer A timer C timer F timer G asynchronous event counter SCI3 IRQAEC IRQ4 IRQ3 IRQ1 IRQ0 WKP7 to WKP0 or by a low...

Page 163: ...Clearing Subactive Mode Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin Clearing by SLEEP instruction If a SLEEP instruction is executed while the SSBY bit in SYSCR1...

Page 164: ...de is cleared by a SLEEP instruction Clearing by SLEEP instruction A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 the LSON bit i...

Page 165: ...m active medium speed mode to active high speed mode When a SLEEP instruction is executed in active medium speed mode while the SSBY and LSON bits in SYSCR1 are cleared to 0 the MSON bit in SYSCR2 is...

Page 166: ...mode A direct transition from active high speed mode to active medium speed mode is performed by executing a SLEEP instruction in active high speed mode while bits SSBY and LSON are both cleared to 0...

Page 167: ...C clock cycle time tcyc System clock cycle time 3 Time for direct transition from subactive mode to active high speed mode A direct transition from subactive mode to active high speed mode is performe...

Page 168: ...ed as the CPU operating clock and wait time 8192 states Legend tosc OSC clock cycle time tw Watch clock cycle time tcyc System clock cycle time tsubcyc Subclock SUB cycle time 5 8 3 Notes on External...

Page 169: ...esponding bit to 1 in clock stop register 1 CKSTPR1 or clock stop register 2 CKSTPR2 See table 5 5 Following a reset clock stop register 1 CKSTPR1 and clock stop register 2 CKSTPR2 are both initialize...

Page 170: ...is cleared 0 Watchdog timer is set to module standby mode AECKSTP 1 Asynchronous event counter module standby mode is cleared 0 Asynchronous event counter is set to module standby mode PW2CKSTP 1 PWM2...

Page 171: ...wo state access for both byte data and word data The H8 38024 has a ZTAT version and F ZTAT version with 32 Kbyte PROM and flash memory A F ZTAT version of the H8 38124 is available and it has 32 Kbyt...

Page 172: ...However page programming is not supported Table 6 1 shows how to set the chip to PROM mode Table 6 1 Setting to PROM Mode Pin Name Setting TEST High level PB0 AN0 Low level PB1 AN1 PB2 AN2 High level...

Page 173: ...n EPROM socket FP 80A TFP 80C FP 80B Pin 12 21 22 23 24 25 26 27 28 69 70 63 64 65 66 67 68 29 72 31 32 33 34 35 57 58 36 30 56 52 1 11 75 54 55 59 53 8 6 73 74 14 23 24 25 26 27 28 29 30 71 72 65 66...

Page 174: ...ea is read in PROM mode Therefore when programming with a PROM programmer be sure to specify addresses from H 0000 to H 7FFF If programming is inadvertently performed from H 8000 onward it may not be...

Page 175: ...and reading are identical to those for the standard HN27C101 EPROM However page programming is not supported and so page programming mode must not be set A PROM programmer that only supports page pro...

Page 176: ...3 V CC PP Address 0 n 0 n 1 n PW Verify Write time t 0 2n ms OPW Last address Set read mode V 5 0 V 0 25 V V V CC PP CC Read all addresses End Error n 25 Address 1 address No Yes No Yes Yes No No Yes...

Page 177: ...Typ Max Unit Test Condition Input high level voltage EO7 to EO0 EA16 to EA0 OE CE PGM VIH 2 4 VCC 0 3 V Input low level voltage EO7 to EO0 EA16 to EA0 OE CE PGM VIL 0 3 0 8 V Output high level voltag...

Page 178: ...up time tVPS 2 s Programming pulse width tPW 0 19 0 20 0 21 ms PGM pulse width for overwrite programming tOPW 3 0 19 5 25 ms CE setup time tCES 2 s VCC setup time tVCS 2 s Data output delay time tOE 0...

Page 179: ...am Write Input data Output data Verify Address Data VPP VPP tAS tAH tDS tDH tDF tOE tOES tPW tOPW tVPS tVCS tCES VCC VCC CE PGM OE VCC 1 VCC Note tOPW is defined by the value shown in figure 6 4 High...

Page 180: ...d chip are properly aligned If they are not the chip may be destroyed by excessive current flow Before programming be sure that the chip is properly mounted in the PROM programmer Avoid touching the s...

Page 181: ...ended screening procedure Program chip and verify programmed data Bake chip for 24 to 48 hours at 125 C to 150 C with power off Read and check program Install Figure 6 6 Recommended Screening Procedur...

Page 182: ...ing can be done in boot mode in which the boot program built into the chip is started to erase or program of the entire flash memory In normal user program mode individual blocks can be erased or prog...

Page 183: ...ce controller Operating mode TES pin P95 pin P34 pin Legend FLMCR1 Flash memory control register 1 FLMCR2 Flash memory control register 2 EBR Erase block register FLPWCR Flash memory power control reg...

Page 184: ...02 H 00FF H 0080 H 0081 H 0082 H 03FF H 0380 H 0381 H 0382 H 047F H 0400 H 0401 H 0402 H 04FF H 0480 H 0481 H 0482 H 07FF H 0780 H 0781 H 0782 H 087F H 0800 H 0801 H 0802 H 08FF H 0880 H 0881 H 0882 H...

Page 185: ...er 2 FLMCR2 R H 00 H F021 Flash memory power control register FLPWCR R W H 00 H F022 Erase block register EBR R W H 00 H F023 Flash memory enable register FENR R W H 00 H F02B Note FLMCR1 FLMCR2 FLPWC...

Page 186: ...eared when using flash memory as normal built in ROM Bit 7 Reserved This bit is always read as 0 and cannot be modified Bit 6 Software Write Enable SWE This bit is to set enabling disabling of program...

Page 187: ...WE ESU PSU PV E and P bits at the same time Bit 3 EV Description 0 Erase verify mode is cancelled initial value 1 The flash memory changes to erase verify mode Bit 2 Program Verify PV This bit is to s...

Page 188: ...ad Write R FLMCR2 is a register that displays the state of flash memory programming erasing FLMCR2 is a read only register and should not be written to Bit 7 Flash Memory Error FLER This bit is set wh...

Page 189: ...are to be erased erase them in turn in unit of a block Table 6 6 Division of Blocks to Be Erased EBR Bit Name Block Size Address 0 EB0 EB0 1 Kbyte H 0000 to H 03FF 1 EB1 EB1 1 Kbyte H 0400 to H 07FF...

Page 190: ...and cannot be modified 6 6 5 Flash Memory Enable Register FENR Bit 7 6 5 4 3 2 1 0 FLSHE Initial value 0 0 0 0 0 0 0 0 Read Write R W FENR controls CPU access to the flash memory control registers FLM...

Page 191: ...states before the reset ends When changing to boot mode the boot program built into this LSI is initiated The boot program transfers the programming control program from the externally connected host...

Page 192: ...one H 55 byte to the chip If reception could not be performed normally initiate boot mode again by a reset Depending on the host s transfer bit rate and system clock frequency of this LSI there will b...

Page 193: ...mber of bytes N of programming control program to be transferred as 2 byte data low order byte following high order byte Transmits 1 byte of programming control program Transfer of programming control...

Page 194: ...rogram from external memory As the flash memory itself cannot be read during programming erasing transfer the user program erase control program to on chip RAM as in boot mode Figure 6 9 shows a sampl...

Page 195: ...ase mode and erase verify mode The programming control program in boot mode and the user program erase control program in user program mode use these operating modes in combination to perform programm...

Page 196: ...The time during which the P bit is set to 1 is the programming time Figure 6 12 shows the allowable programming times 6 The watchdog timer WDT is set to prevent overprogramming due to program runaway...

Page 197: ...Reprogram data computation Clear PV bit in FLMCR1 Clear SWE bit in FLMCR1 Increment address Programming failure Clear SWE bit in FLMCR1 Wait 100 s No Yes No Yes No Wait 100 s n 1000 Write 128 byte dat...

Page 198: ...ased state Table 6 11 Additional Program Data Computation Table Reprogram Data Verify Data Additional Program Data Comments 0 0 0 Additional program bit 0 1 1 No additional programming 1 0 1 No additi...

Page 199: ...a dummy write was performed Do not use RTS instruction from dummy write to verify data read This does not apply to the HD64F38124 6 If the read data is not erased successfully set erase mode again and...

Page 200: ...ify data Increment address Verify data all 1s Last address of block All erase block erased Set block start address as verify address H FF dummy write to verify address Wait 20 s Wait 2 s EV bit 1 Wait...

Page 201: ...ng the erase block register EBR erase protection can be set for individual blocks When EBR is set to H 00 erase protection is set for all blocks 6 9 3 Error Protection In error protection an error is...

Page 202: ...cket adapter pin correspondence diagram of the HD64F38124 6 10 2 Programmer Mode Commands The following commands are supported in programmer mode Memory Read Mode Auto Program Mode Auto Erase Mode Sta...

Page 203: ...1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 FWE A9 A16 A15 WE I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE Vcc...

Page 204: ...I O2 I O3 I O4 I O5 I O6 I O7 A0 A1 A2 A3 A4 A5 A6 A7 A8 OE A10 A11 A12 A13 A14 CE Vcc Vss 30 36 56 21 22 23 24 25 26 27 28 69 70 63 64 65 66 67 68 29 71 31 32 33 34 35 72 52 1 6 11 51 52 58 4 59 8 53...

Page 205: ...tate 3 After powering on memory read mode is entered 4 Tables 6 14 to 6 16 show the AC characteristics Table 6 14 AC Characteristics in Transition to Memory Read Mode Conditions VCC 3 3 V 0 3 V VSS 0...

Page 206: ...ure 6 14 CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns CE A15 A0 OE WE I O7...

Page 207: ...re 6 16 OE output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns CE A15 A0 OE WE I O7 I O0 tacc tacc toh toh Address stable Address stable Figure 6 15 CE CE...

Page 208: ...input processing will switch to a memory write operation but a write error will be flagged 5 Memory address transfer is performed in the second cycle figure 6 17 Do not perform transfer after the thir...

Page 209: ...pulse width twep 70 ns Status polling start time twsts 1 ms Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms WE rise ti...

Page 210: ...next command write As long as the next command write has not been performed reading is possible by enabling CE and OE 5 Table 6 18 shows the AC characteristics Table 6 18 AC Characteristics in Auto E...

Page 211: ...e return code is retained until a command write other than a status read mode command write is executed 3 Table 6 19 shows the AC characteristics and 6 20 shows the return codes Table 6 19 AC Characte...

Page 212: ...d Figure 6 19 Status Read Mode Timing Waveforms Table 6 20 Status Read Mode Return Codes Pin Name Initial Value Indications I O7 0 1 Abnormal end 0 Normal end I O6 0 1 Command error 0 Otherwise I O5 0...

Page 213: ...e Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period After the programmer mode setup time a transition is made to memory read mode Table 6 22 S...

Page 214: ...w power consumption Standby mode All flash memory circuits are halted Table 6 23 shows the correspondence between the operating modes of this LSI and the flash memory In subactive mode the flash memor...

Page 215: ...cted to the CPU by a 16 bit data bus allowing high speed 2 state access for both byte data and word data Note Mask ROM versions of the H8 38124 H8 38123 H8 38122 H8 3811 and H8 38120 are under develop...

Page 216: ...Rev 6 00 08 04 page 186 of 628...

Page 217: ...also used as liquid crystal display segment and common pins selectable in 4 bit units Block diagrams of each port are given in Appendix C I O Port Block Diagrams Table 8 1 Port Functions Port Descrip...

Page 218: ...P92 P95 P94 P92 P93 Vref 4 None LVD reference voltage external input pin 4 LVDSR 4 Dedicated 6 bit output port High voltage large current port 3 P91 P90 PWM2 PWM1 10 bit PWM output PMR9 High voltage...

Page 219: ...mented on the H8 38124 Group Figure 8 1 Port 1 Pin Configuration 8 2 2 Register Configuration and Description Table 8 2 shows the port 1 register configuration Table 8 2 Port 1 Registers Name Abbr R W...

Page 220: ...mented on the H8 38124 Group Port Control Register 1 PCR1 Bit 7 6 5 4 3 2 1 0 PCR17 PCR16 PCR14 PCR13 Initial value 0 0 0 0 Read Write W W W W W W W W PCR1 is an 8 bit register for controlling whether...

Page 221: ...rt Mode Register 1 PMR1 Bit 7 6 5 4 3 2 1 0 IRQ3 IRQ4 TMIG Initial value 0 1 0 0 1 Read Write R W W R W R W W W PMR1 is an 8 bit read write register controlling the selection of pin functions for port...

Page 222: ...value 1 Functions as TMIG input pin Bits 2 and 0 Reserved These bits are reserved they can only be written with 0 Bit 1 Reserved This bit is reserved it is always read as 1 and cannot be modified Port...

Page 223: ...roup Bit 2 WDCKS Description 0 Selects 8192 initial value 1 Selects W 32 H8 38124 Group Bit 2 WDCKS Description 0 Selects clock based on timer mode register W TMW setting initial value 1 Selects W 32...

Page 224: ...the IRQ3 interrupt P16 The pin function depends on bit PCR16 in PCR1 PCR16 0 1 Pin function P16 input pin P16 output pin Note Pin 16 and the associated function are not implemented on the H8 38124 Gro...

Page 225: ...unctional Functional Notes 1 Pin 16 and the associated function are not implemented on the H8 38124 Group 2 A high level signal is output when the MOS pull up is in the on state 8 2 5 MOS Input Pull U...

Page 226: ...Port 3 Pin Configuration 8 3 2 Register Configuration and Description Table 8 5 shows the port 3 register configuration Table 8 5 Port 3 Registers Name Abbr R W Initial Value Address Port data regist...

Page 227: ...the port 3 pins P37 to P30 functions as an input pin or output pin Setting a PCR3 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin The setting...

Page 228: ...IRQ0 pin functions Upon reset PMR2 is initialized to H D8 This section only deals with the bit that controls whether the PMOS transistor internal to pin P35 is on or off For the functions of the othe...

Page 229: ...AEVL Description 0 Functions as P37 I O pin initial value 1 Functions as AEVL input pin Bit 6 P36 AEVH Pin Function Switch AEVH This bit selects whether pin P36 AEVH is used as P36 or as AEVH Bit 6 A...

Page 230: ...is used as P31 or as TMOFL Bit 1 TMOFL Description 0 Functions as P31 I O pin initial value 1 Functions as TMOFL output pin Bit 0 P30 UD Pin Function Switch UD This bit selects whether pin P30 UD is...

Page 231: ...pin P36 output pin AEVH input pin P35 to P33 The pin function depends on the corresponding bit in PCR3 PCR3n 0 1 Pin function P3n input pin P3n output pin n 5 to 3 P32 TMOFH The pin function depends o...

Page 232: ...revious state High impedance Retains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 3 5 MOS Input Pull Up Port 3 has a built in MOS i...

Page 233: ...al Value Address Port data register 4 PDR4 R W H F8 H FFD7 Port control register 4 PCR4 W H F8 H FFE7 Port mode register 2 PMR2 R W H D8 H FFC9 Port Data Register 4 PDR4 Bit Initial value Read Write 7...

Page 234: ...ll 1s Port Mode Register 2 PMR2 Bit Initial value Read Write 7 1 6 1 5 POF1 0 R W 4 1 3 1 0 IRQ0 0 R W 2 WDCKS 0 R W 1 NCS 0 R W PMR2 is an 8 bit read write register It controls whether the PMOS trans...

Page 235: ...E in SCR3 bit SPC32 in SPCR and bit PCR42 in PCR4 SPC32 0 1 TE 0 1 PCR42 0 1 Pin function P42 input pin P42 output pin TXD32 output pin P41 RXD32 The pin function depends on bit RE in SCR3 and bit PCR...

Page 236: ...n states in each operating mode Table 8 10 Port 4 Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active P43 IRQ0 P42 TXD32 P41 RXD32 P40 SCK32 High impedance Retains previous state Retai...

Page 237: ...WKP1 SEG2 P50 WKP0 SEG1 Port 5 Figure 8 4 Port 5 Pin Configuration 8 5 2 Register Configuration and Description Table 8 11 shows the port 5 register configuration Table 8 11 Port 5 Registers Name Abbr...

Page 238: ...P57 to P50 functions as an input pin or output pin Setting a PCR5 bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin PCR5 and PDR5 settings are...

Page 239: ...olling the selection of pin functions for port 5 pins Upon reset PMR5 is initialized to H 00 Bit n P5n WKP WKP WKP WKPn SEGn 1 Pin Function Switch WKPn When pin P5n WKPn SEGn 1 is not used as SEGn 1 t...

Page 240: ...to SGS0 in LPCR P50 WKP0 SEG1 P57 to P54 n 7 to 4 SGS3 to SGS0 Other than 0010 0011 0100 0101 0110 0111 1000 1001 0010 0011 0100 0101 0110 0111 1000 1001 WKPn 0 1 PCR5n 0 1 Pin function P5n input pin...

Page 241: ...evious state Functional Functional Note A high level signal is output when the MOS pull up is in the on state In the HD64F38024 the previous pin state is retained 8 5 5 MOS Input Pull Up Port 5 has a...

Page 242: ...3 SEG12 P62 SEG11 P61 SEG10 P60 SEG9 Port 6 Figure 8 5 Port 6 Pin Configuration 8 6 2 Register Configuration and Description Table 8 14 shows the port 6 register configuration Table 8 14 Port 6 Regist...

Page 243: ...s initialized to H 00 Port Control Register 6 PCR6 Bit Initial value Read Write 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 PCR63 0 W 0 PCR60 0 W 2 PCR62 0 W 1 PCR61 0 W PCR6 is an 8 bit registe...

Page 244: ...ull up Upon reset PUCR6 is initialized to H 00 8 6 3 Pin Functions Table 8 15 shows the port 6 pin functions Table 8 15 Port 6 Pin Functions Pin Pin Functions and Selection Method P67 SEG16 to P60 SEG...

Page 245: ...High impedance Retains previous state Functional Functional Note A high level signal is output when the MOS pull up is in the on state 8 6 5 MOS Input Pull Up Port 6 has a built in MOS pull up functio...

Page 246: ...SEG22 P74 SEG21 P73 SEG20 Port 7 P72 SEG19 P71 SEG18 P70 SEG17 Figure 8 6 Port 7 Pin Configuration 8 7 2 Register Configuration and Description Table 8 17 shows the port 7 register configuration Table...

Page 247: ...is initialized to H 00 Port Control Register 7 PCR7 Bit Initial value Read Write 7 PCR7 0 W 6 PCR7 0 W 5 PCR7 0 W 4 PCR7 0 W 3 PCR7 0 W 0 PCR7 0 W 2 PCR7 0 W 1 PCR7 0 W 7 6 5 4 3 2 1 0 PCR7 is an 8 bi...

Page 248: ...1101 PCR7n 0 1 Pin function P7n input pin P7n output pin SEGn 17 output pin P73 to P70 m 3 to 0 SGS3 to SGS0 Other than 0101 0110 0111 1000 1001 1010 1011 1100 0101 0110 0111 1000 1001 1010 1011 1100...

Page 249: ...SEG30 P84 SEG29 P83 SEG28 P82 SEG27 P81 SEG26 P80 SEG25 Port 8 Figure 8 7 Port 8 Pin Configuration 8 8 2 Register Configuration and Description Table 8 20 shows the port 8 register configuration Table...

Page 250: ...t PDR8 is initialized to H 00 Port Control Register 8 PCR8 Bit Initial value Read Write 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W 0 PCR80 0 W 2 PCR82 0 W 1 PCR81 0 W PCR8 is an 8 bit...

Page 251: ...1111 PCR8n 0 1 Pin function P8n input pin P8n output pin SEGn 25 output pin P83 to P80 m 3 to 0 SGS3 to SGS0 Other than 0111 1000 1001 1010 1011 1100 1101 1110 0111 1000 1001 1010 1011 1100 1101 1110...

Page 252: ...ration 8 9 2 Register Configuration and Description Table 8 23 shows the port 9 register configuration Table 8 23 Port 9 Registers Name Abbr R W Initial Value Address Port data register 9 PDR9 R W H F...

Page 253: ...F to 0 and then after waiting 30 system clock cycles turn on the buffer NMOS port data cleared to 0 If 30 system clock cycles have not elapsed the voltage boost circuit will not start operating and it...

Page 254: ...to 0 only when the PIOFF bit is cleared to 0 Also if a large current flow is required the PIOFF bit should be set to 1 and all the port data bits set to 1 Then clear PIOFF to 0 and after allowing 30...

Page 255: ...VCSS1 0 1 Pin function P93 output pin Vref input pin n 1 or 0 P91 PWMn 1 to P90 PWMn 1 PMR9n 0 1 Pin function P9n output pin PWMn 1 output pin Note The Vref pin is the input pin for the LVD s externa...

Page 256: ...W Initial Value Address Port data register A PDRA R W H F0 H FFDD Port control register A PCRA W H F0 H FFED Port Data Register A PDRA Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 PA 0 R W 0 PA 0 R...

Page 257: ...pins PA3 to PA0 functions as an input pin or output pin Setting a PCRA bit to 1 makes the corresponding pin an output pin while clearing the bit to 0 makes the pin an input pin PCRA and PDRA settings...

Page 258: ...in PA2 COM3 The pin function depends on bit PCRA2 in PCRA and bits SGS3 to SGS0 SGS3 to SGS0 0000 0000 Not 0000 PCRA2 0 1 Pin function PA2 input pin PA2 output pin COM3 output pin PA1 COM2 The pin fun...

Page 259: ...pin states in each operating mode Table 8 28 Port A Pin States Pins Reset Sleep Subsleep Standby Watch Subactive Active PA3 COM4 PA2 COM3 PA1 COM2 PA0 COM1 High impedance Retains previous state Retain...

Page 260: ...extD pins are implemented on the H8 38124 Group only Figure 8 10 Port B Pin Configuration 8 11 2 Register Configuration and Description Table 8 29 shows the port B register configuration Table 8 29 P...

Page 261: ...pin function Upon reset PMRB is initialized to H F7 Bits 7 to 4 and 2 to 0 Reserved Bits 7 to 4 and 2 to 0 are reserved they are always read as 1 and cannot be modified Bit 3 PB3 AN3 IRQ IRQ IRQ IRQ1...

Page 262: ...MR CH3 to CH0 Not 1001 1001 Pin function PB5 input pin AN5 input pin PB4 AN4 The pin function depends on bits CH3 to CH0 in AMR CH3 to CH0 Not 1000 1000 Pin function PB4 input pin AN4 input pin PB3 AN...

Page 263: ...Group only PB0 AN0 extD Switching is accomplished by combining CH3 to CH0 in AMR and VINTDSEL in LVDCR as shown below Note that VINTDSEL is implemented on the H8 38124 Group only VINTDSEL 0 1 CH3 to...

Page 264: ...W 0 W 2 SCINV2 0 R W 1 W SPCR is an 8 bit readable writable register that performs RXD32 and TXD32 pin input output data inversion switching Bits 7 and 6 Reserved Bits 7 and 6 are reserved they are al...

Page 265: ...s to be inverted Bit 2 SCINV2 Description 0 RXD32 input data is not inverted initial value 1 RXD32 input data is inverted Bits 1 and 0 Reserved Bits 1 and 0 are reserved they can only be written with...

Page 266: ...pproximately 100 k Pull it down to VSS with an external resistor of approximately 100 k For a pin also used by the A D converter pull it up to AVCC If an unused pin is an output pin handle it in one o...

Page 267: ...nterval function Event counting function Up count down count selectable 4 to 8192 W 4 7 choices TMIC Up count down count controllable by software or hardware Timer F 16 bit timer Event counting functi...

Page 268: ...4 Group See section 9 6 Watchdog Timer for details 9 2 Timer A 9 2 1 Overview Timer A is an 8 bit timer with interval timing and real time clock time base functions The clock time base function is ava...

Page 269: ...1 4 TMA TCA 8192 4096 2048 512 256 128 32 8 IRRTA 8 64 128 256 W 4 W 128 TMA TCA IRRTA PSW PSS Note Can be selected only when the prescaler W output W 128 is used as the TCA input clock Timer mode reg...

Page 270: ...B1 Clock stop register 1 CKSTPR1 R W H FF H FFFA 9 2 2 Register Descriptions Timer Mode Register A TMA Bit Initial value Read Write 7 W 6 W 5 W 4 1 3 TMA3 0 R W 0 TMA0 0 R W 2 TMA2 0 R W 1 TMA1 0 R W...

Page 271: ...tion Bit 3 TMA3 Bit 2 TMA2 Bit 1 TMA1 Bit 0 TMA0 Prescaler and Divider Ratio or Overflow Period Function 0 0 0 0 PSS 8192 initial value Interval timer 1 PSS 4096 1 0 PSS 2048 1 PSS 512 1 0 0 PSS 256 1...

Page 272: ...TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11 Upon reset TCA is initialized to H 00 Clock Stop Register 1 CKSTPR1 TFCKSTP TCCKSTP TACKSTP S32CKSTP ADCKSTP TGCKSTP 7 6 5 4 3 2 1 0 1 1 1 1 1...

Page 273: ...pts Real Time Clock Time Base Operation When bit TMA3 in TMA is set to 1 timer A functions as a real time clock time base by counting clock signals output by prescaler W The overflow period of timer A...

Page 274: ...a clock pulse is input This timer has two operation modes interval and auto reload Features Features of timer C are given below Choice of seven internal clock sources 8192 2048 512 64 16 4 W 4 or an e...

Page 275: ...register C Timer counter C Timer load register C Timer C overflow interrupt request flag Prescaler S Figure 9 2 Block Diagram of Timer C Pin Configuration Table 9 4 shows the timer C pin configuratio...

Page 276: ...r Descriptions Timer Mode Register C TMC Bit Initial value Read Write 7 TMC7 0 R W 6 TMC6 0 R W 5 TMC5 0 R W 4 1 3 1 0 TMC0 0 R W 2 TMC2 0 R W 1 TMC1 0 R W TMC is an 8 bit read write register for sele...

Page 277: ...e modified Bits 2 to 0 Clock Select TMC2 to TMC0 Bits 2 to 0 select the clock input to TCC For external event counting either the rising or falling edge can be selected Bit 2 TMC2 Bit 1 TMC1 Bit 0 TMC...

Page 278: ...the IRRTC bit in IRR2 is set to 1 TCC is allocated to the same address as TLC Upon reset TCC is initialized to H 00 Timer Load Register C TLC Bit Initial value Read Write 7 TLC7 0 W 6 TLC6 0 W 5 TLC5...

Page 279: ...unctions as an 8 bit interval timer Upon reset TCC is initialized to H 00 and TMC to H 18 so TCC continues up counting as an interval up counter without halting immediately after a reset The timer C o...

Page 280: ...ode In auto reload mode TMC7 1 when a new value is set in TLC the TLC value is also set in TCC Event Counter Operation Timer C can operate as an event counter counting rising or falling edges of an ex...

Page 281: ...te When w 4 is selected as the TCC internal clock in active mode or sleep mode since the system clock and internal clock are mutually asynchronous synchronization is maintained by a synchronization ci...

Page 282: ...al Two interrupt sources one compare match one overflow Can operate as two independent 8 bit timers timer FH and timer FL in 8 bit mode Timer FH 8 Bit Timer Timer FL 8 Bit Timer Event Counter Internal...

Page 283: ...rator Comparator Match IRRTFH IRRTFL Legend TCRF TCSRF TCFH TCFL OCRFH OCRFL IRRTFH IRRTFL PSS Timer control register F Timer control status register F 8 bit timer counter FH 8 bit timer counter FL Ou...

Page 284: ...imer FL toggle output pin Register Configuration Table 9 8 shows the register configuration of timer F Table 9 8 Timer F Registers Name Abbr R W Initial Value Address Timer control register F TCRF W H...

Page 285: ...Interface TCFH and TCFL are each initialized to H 00 upon reset a 16 bit mode TCF When CKSH2 is cleared to 0 in TCRF TCF operates as a 16 bit counter The TCF input clock is selected by bits CKSL2 to C...

Page 286: ...o H FF upon reset a 16 bit mode OCRF When CKSH2 is cleared to 0 in TCRF OCRF operates as a 16 bit register OCRF contents are constantly compared with TCF and when both values match CMFH is set to 1 in...

Page 287: ...on reset Bit 7 Toggle Output Level H TOLH Bit 7 sets the TMOFH pin output level The output level is effective immediately after this bit is written Bit 7 TOLH Description 0 Low level initial value 1 H...

Page 288: ...0 Description 0 0 0 0 0 1 Counting on external event TMIF rising falling edge initial value 0 1 0 0 1 1 Use prohibited 1 0 0 Internal clock counting on 32 1 0 1 Internal clock counting on 16 1 1 0 Int...

Page 289: ...er Overflow Flag H OVFH Bit 7 is a status flag indicating that TCFH has overflowed from H FF to H 00 This flag is set by hardware and cleared by software It cannot be set by software Bit 7 OVFH Descri...

Page 290: ...hen TCFH and OCRFH match Bit 4 CCLRH Description 0 16 bit mode TCF clearing by compare match is disabled 8 bit mode TCFH clearing by compare match is disabled initial value 1 16 bit mode TCF clearing...

Page 291: ...dition Set when the TCFL value matches the OCRFL value Bit 1 Timer Overflow Interrupt Enable L OVIEL Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows Bit 1 OVIEL Descrip...

Page 292: ...Interface TCF and OCRF are 16 bit read write registers but the CPU is connected to the on chip peripheral modules by an 8 bit data bus When the CPU accesses these registers it therefore uses an 8 bit...

Page 293: ...example in which H AA55 is written to TCF Write to upper byte CPU H AA TEMP H AA TCFH TCFL Bus interface Module data bus Write to lower byte CPU H 55 TEMP H AA TCFH H AA TCFL H 55 Bus interface Modul...

Page 294: ...CRF when the upper byte is read the upper byte data is transferred directly to the CPU When the lower byte is read the lower byte data is transferred directly to the CPU Figure 9 5 shows an example in...

Page 295: ...put by prescaler S or an external clock by means of bits CKSL2 to CKSL0 in TCRF OCRF contents are constantly compared with TCF and when both values match CMFH is set to 1 in TCSRF If IENTFH in IENR2 i...

Page 296: ...n increment on either the rising or falling edge of external event input External event edge selection is set by IEG3 in the interrupt controller s IEGR register An external event pulse width of at le...

Page 297: ...Timer F Operation Modes Operation Mode Reset Active Sleep Watch Sub active Sub sleep Standby Module Standby TCF Reset Functions Functions Functions Halted Functions Halted Functions Halted Halted Hal...

Page 298: ...Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied When TCF overflows OVFH is set OVFL is set if the setting conditions are satisfied when the lower 8 bits ove...

Page 299: ...you cannot be cleared timer overflow flag and compare match flag during the term of validity of Overflow signal and Compare match signal For interrupt request flag is set right after interrupt reques...

Page 300: ...mode Program process W Interrupt request flag IRRTFH IRRTFL Interrupt factor generation signal Internal signal nega active Overflow signal Compare match signal Internal signal nega active Interrupt I...

Page 301: ...capture functions for rising and falling edges Level detection at counter overflow It is possible to detect whether overflow occurred when the input capture input signal was high or when it was low S...

Page 302: ...Noise canceler Edge detector Level detector IRRTG W 4 TMIG NCS Legend TMG TCG ICRGF ICRGR IRRTG NCS PSS Timer mode register G Timer counter G Input capture register GF Input capture register GR Timer...

Page 303: ...ister Descriptions Timer Counter G TCG TCG7 TCG2 TCG1 TCG0 TCG6 TCG5 TCG4 TCG3 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Bit Initial value Read Write TCG is an 8 bit up counter which is incremented by clock inp...

Page 304: ...dependable input capture operation the pulse width of the input capture input signal must be at least 2 or 2 SUB when the noise canceler is not used ICRGF is initialized to H 00 upon reset Input Captu...

Page 305: ...H OVFH Bit 7 is a status flag indicating that TCG has overflowed from H FF to H 00 when the input capture input signal is high This flag is set by hardware and cleared by software It cannot be set by...

Page 306: ...capture input signal Bits 3 and 2 Counter Clear 1 and 0 CCLR1 CCLR0 Bits 3 and 2 specify whether or not TCG is cleared by the rising edge falling edge or both edges of the input capture input signal...

Page 307: ...ister that performs module standby mode control for peripheral modules Only the bit relating to timer G is described here For details of the other bits see the sections on the relevant modules Bit 3 T...

Page 308: ...rnal clock selected by CKS1 and CKS0 in TMG the input capture input is sampled on the rising edge of this clock and the data is judged to be correct when all the latch outputs match If all the outputs...

Page 309: ...Rev 6 00 08 04 page 279 of 628 Input capture input signal Sampling clock Noise canceler output Eliminated as noise Figure 9 10 Noise Canceler Timing Example...

Page 310: ...s of the interrupt see section 3 3 Interrupts TCG can be cleared by a rising edge falling edge or both edges of the input capture signal according to the setting of bits CCLR1 and CCLR0 in TMG If TCG...

Page 311: ...tion function For input capture input dedicated input capture functions are provided for rising and falling edges Figure 9 11 shows the timing for rising falling edge input capture input Input capture...

Page 312: ...Input capture signal R Figure 9 12 Input Capture Input Timing with Noise Cancellation Function Timing of Input Capture by Input Capture Input Figure 9 13 shows the timing of input capture by input ca...

Page 313: ...eared by the rising edge falling edge or both edges of the input capture input signal Figure 9 14 shows the timing for clearing by both edges Input capture input signal Input capture signal F Input ca...

Page 314: ...lock in watch mode TCG and the noise canceler operate on the w 4 internal clock without regard to the SUB subclock w 8 w 4 w 2 Note that when another internal clock is selected TCG and the noise cance...

Page 315: ...low level to low level Clock before switching Clock after switching Count clock TCG N N 1 Write to CKS1 and CKS0 2 Goes from low level to high level Clock before switching Clock after switching Count...

Page 316: ...ut signal input edges and the conditions for their occurrence are summarized in table 9 14 Table 9 14 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching and Conditions for...

Page 317: ...capture input signal input edges and the conditions for their occurrence are summarized in table 9 15 Table 9 15 Input Capture Input Signal Input Edges Due to Noise Canceler Function Switching and Co...

Page 318: ...sampling clocks when the noise canceler is used before clearing the interrupt enable flag to 0 There are two ways of preventing interrupt request flag setting when the pin function is switched by cont...

Page 319: ...s of the input capture input signal as absolute values For this purpose CCLR1 and CCLR0 in TMG should both be set to 1 Figure 9 16 shows an example of the operation in this case Counter cleared TCG H...

Page 320: ...atchdog timer are given below Incremented by internal clock source 8192 or w 32 on the H8 38024 H8 38024S and H8 38024F ZTAT Group On the H8 38124 Group 10 internal clocks 64 128 256 512 1024 2048 409...

Page 321: ...2 show a block diagram of the watchdog timer PSS TCSRW TCW 8192 Legend TCSRW TCW PSS W 32 Internal data bus Reset signal Timer control status register W Timer counter W Prescaler S Figure 9 17 1 Bloc...

Page 322: ...17 2 Block Diagram of Watchdog Timer H8 38124 Group Register Configuration Table 9 16 shows the register configuration of the watchdog timer Table 9 16 Watchdog Timer Registers Name Abbr R W Initial V...

Page 323: ...up initial value is 1 on H8 38124 Group TCSRW is an 8 bit read write register that controls write access to TCW and TCSRW itself controls watchdog timer operations and indicates operating status Bit 7...

Page 324: ...t 4 Timer Control Status Register W Write Enable TCSRWE Bit 4 controls the writing of data to bits 2 and 0 in TCSRW Bit 4 TCSRWE Description 0 Data cannot be written to bits 2 and 0 initial value 1 Da...

Page 325: ...and 1 is written to WDON Counting starts when this bit is set to 1 and stops when this bit is cleared to 0 Bit 1 Bit 0 Write Inhibit B0WI Bit 1 controls the writing of data to bit 0 in TCSRW Bit 1 B0W...

Page 326: ...is set to 1 in TCSRW Upon reset TCW is initialized to H 00 Timer Mode Register TMW Bit 7 6 5 4 3 2 1 0 CKS3 CKS2 CKS1 CKS0 Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W The TMW register is...

Page 327: ...by mode control for peripheral modules Only the bit relating to the watchdog timer is described here For details of the other bits see the sections on the relevant modules Bit 2 Watchdog Timer Module...

Page 328: ...ed here For details of the other bits see section 8 I O Ports Bit 2 Watchdog Timer Source Clock Select WDCKS This bit selects the watchdog timer source clock Note that stabilization times for the H8 3...

Page 329: ...1 after a reset is cancelled TCW starts to be incremented even without gaining write access to TCSRW When the TCW count value reaches H FF the next clock input causes the watchdog timer to overflow a...

Page 330: ...alted Retained Retained Retained Note Functions when w 32 is selected as the input clock Table 9 17 2 Watchdog Timer Operation States H8 38124 Group Operation Mode Reset Active Sleep Watch Subactive S...

Page 331: ...n IRQAEC is high or event counter PWM output IECPWM is high Both edge sensing can be used for IRQAEC or event counter PWM output IECPWM interrupts When the asynchronous counter is not used independent...

Page 332: ...circuit Edge sensing circuit Edge sensing circuit PWM waveform generator 2 4 8 2 4 8 16 32 64 Legend ECPWCRH Event counter PWM compare register H ECPWDRH Event counter PWM data register H AEGSR Input...

Page 333: ...ows the register configuration of the asynchronous event counter Table 9 19 Asynchronous Event Counter Registers Name Abbr R W Initial Value Address Event counter PWM compare register H ECPWCRH R W H...

Page 334: ...AEGSR before modifying ECPWCRH ECPWCRH is an 8 bit read write register that sets the event counter PWM waveform conversion period Event Counter PWM Compare Register L ECPWCRL Bit Initial value Read W...

Page 335: ...PWDRL Bit Initial value Read Write 7 ECPWDRL7 0 W 6 ECPWDRL6 0 W 5 ECPWDRL5 0 W 4 ECPWDRL4 0 W 3 ECPWDRL3 0 W 0 ECPWDRL0 0 W 2 ECPWDRL2 0 W 1 ECPWDRL1 0 W Note When ECPWME in AEGSR is 1 event counter...

Page 336: ...its 5 and 4 select rising falling or both edge sensing for the AEVL pin Bit 5 ALEGS1 Bit 4 ALEGS0 Description 0 0 Falling edge on AEVL pin is sensed initial value 1 Rising edge on AEVL pin is sensed 1...

Page 337: ...readable writable reserved bit It is initialized to 0 by a reset Note Do not set this bit to 1 Event Counter Control Register ECCR Bit Initial value Read Write 7 ACKH1 0 R W 6 ACKH0 0 R W 5 ACKL1 0 R...

Page 338: ...put initial value 1 2 1 0 4 1 8 Bits 3 to 1 Event Counter PWM Clock Select PWCK2 PWCK1 PWCK0 Bits 3 to 1 select the event counter PWM clock Bit 3 PWCK2 Bit 2 PWCK1 Bit 1 PWCK0 Description 0 0 0 2 init...

Page 339: ...verflows It is cleared by software but cannot be set by software OVH is cleared by reading it when set to 1 then writing 0 When ECH and ECL are used as a 16 bit event counter with CH2 cleared to 0 OVH...

Page 340: ...ignal from ECL is selected as the ECH input clock When CH2 is set to 1 ECH and ECL function as independent 8 bit event counters which are incremented each time an event clock is input to the AEVH or A...

Page 341: ...iption 0 ECH is reset initial value 1 ECH reset is cleared and count up function is enabled Bit 0 Counter Reset Control L CRCL Bit 0 controls resetting of ECL When this bit is cleared to 0 ECL is rese...

Page 342: ...also initialized to H 00 upon reset Clock Stop Register 2 CKSTPR2 LVDCKSTP WDCKSTP PW1CKSTP LDCKSTP PW2CKSTP AECKSTP 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 R W R W R W R W R W R W Bit Initial value Read Writ...

Page 343: ...er Start End Clear CH2 to 0 Set ACKL1 ACKL0 ALEGS1 and ALEGS0 Clear CUEH CUEL CRCH and CRCL to 0 Clear OVH and OVL to 0 Set CUEH CUEL CRCH and CRCL to 1 Figure 9 20 Example of Software Processing when...

Page 344: ...tware processing when ECH and ECL are used as 8 bit event counters Start End Set CH2 to 1 Set ACKH1 ACKH0 ACKL1 ACKL0 AHEGS1 AHEGS0 ALEGS1 and ALEGS0 Clear CUEH CUEL CRCH and CRCL to 0 Clear OVH to 0...

Page 345: ...l of switching between the system clock oscillator and the on chip oscillator during resets should be performed by setting the IRQAEC input level Refer to section 4 Clock Pulse Generators for details...

Page 346: ...peed active mode ECPWCR value Ncm H 7A11 ECPWDR value Ndr H 16E3 Clock Source Selection Clock Source Cycle T ECPWCR Value Ncm ECPWDR Value Ndr toff T Ndr 1 tcm T Ncm 1 ton tcm toff 2 1 s 5 86 ms 31 25...

Page 347: ...Functions Retained 1 Functions Functions Retained 1 Retained ECCSR Reset Functions Functions Retained 1 Functions Functions Retained 1 Retained ECH Reset Functions Functions Functions 1 2 Functions 2...

Page 348: ...kHz 250 kHz 3 When using the clock in the 16 bit mode set CUEH to 1 first then set CRCH to 1 in ECCSR Or set CUEH and CRCH simultaneously before inputting the clock After that do not change the CUEH...

Page 349: ...cter In this mode serial data can be exchanged with standard asynchronous communication LSIs such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter...

Page 350: ...ouble buffered allowing continuous transmission and reception On chip baud rate generator allowing any desired bit rate to be selected Choice of an internal or external clock as the transmit receive c...

Page 351: ...egend RSR RDR TSR TDR SMR SCR3 SSR BRR BRC SPCR Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register 3 Serial status...

Page 352: ...able 10 2 shows the SCI3 register configuration Table 10 2 Registers Name Abbr R W Initial Value Address Serial mode register SMR R W H 00 H FFA8 Bit rate register BRR R W H FF H FFA9 Serial control r...

Page 353: ...ten directly by the CPU 10 2 2 Receive Data Register RDR Bit Initial value Read Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R 0 RDR0 0 R 2 RDR2 0 R 1 RDR1 0 R RDR is an 8 bit register t...

Page 354: ...ritten to TDR if bit TDRE is set to 1 in the serial status register SSR TSR cannot be read or written directly by the CPU 10 2 4 Transmit Data Register TDR Bit Initial value Read Write 7 TDR7 1 R W 6...

Page 355: ...ication Mode COM Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode Bit 7 COM Description 0 Asynchronous mode initial value 1 Synchronous mode Bit 6 Character Length CHR Bit...

Page 356: ...d for parity addition and checking The PM bit setting is only valid in asynchronous mode when bit PE is set to 1 enabling parity bit addition and checking The PM bit setting is invalid in synchronous...

Page 357: ...espective of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit but if 0 it is treated as the start bit of the next transmit character Bit 2 Multiprocessor Mode MP Bit 2 enab...

Page 358: ...speed mode and sleep mode 2 w clock in subactive mode and subsleep mode In subactive or subsleep mode SCI3 can be operated when CPU clock is w 2 only 10 2 6 Serial Control Register 3 SCR3 Bit Initial...

Page 359: ...serial status register SSR is set to 1 There are three kinds of receive error overrun framing and parity RXI and ERI can be released by clearing bit RDRF or the FER PER or OER error flag to 0 or by c...

Page 360: ...IE bit setting is only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR set to 1 The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared t...

Page 361: ...in or a clock input pin The CKE0 bit setting is only valid in case of internal clock operation CKE1 0 in asynchronous mode In synchronous mode or when external clock operation is used CKE1 1 bit CKE0...

Page 362: ...Bits TEND and MPBR are read only bits and cannot be modified SSR is initialized to H 84 upon reset and in standby module standby or watch mode Bit 7 Transmit Data Register Empty TDRE Bit 7 indicates...

Page 363: ...ta reception is completed while bit RDRF is still set to 1 an overrun error OER will result and the receive data will be lost Bit 5 Overrun Error OER Bit 5 indicates that an overrun error has occurred...

Page 364: ...s not set Reception cannot be continued with bit FER set to 1 In synchronous mode neither transmission nor reception is possible when bit FER is set to 1 Bit 3 Parity Error PER Bit 3 indicates that a...

Page 365: ...character during multiprocessor format reception in asynchronous mode Bit 1 is a read only bit and cannot be modified Bit 1 MPBR Description 0 Data in which the multiprocessor bit is 0 has been recei...

Page 366: ...by module standby or watch mode Table 10 3 shows examples of BRR settings in asynchronous mode The values shown are for active high speed mode Table 10 3 Examples of BRR Settings for Various Bit Rates...

Page 367: ...6 31250 0 4 0 0 7 0 38400 0 3 1 73 Notes No indication Setting not possible Setting possible but errors may result 1 The value set in BRR is given by the following equation OSC N 64 2 2n B 1 where B B...

Page 368: ...ode and subsleep mode In subactive or subsleep mode SCI3 can be operated when CPU clock is w 2 only Table 10 5 shows the maximum bit rate for each frequency The values shown are for active high speed...

Page 369: ...ed mode Table 10 6 Examples of BRR Settings for Various Bit Rates Synchronous Mode 1 OSC 38 4 kHz 2 MHz 4 MHz Bit Rate bit s n N Error n N Error n N Error 200 0 23 0 250 2 124 0 300 2 0 0 500 1K 0 249...

Page 370: ...24 0 0 199 0 25K 0 49 0 0 79 0 50K 0 24 0 0 39 0 100K 0 19 0 250K 0 4 0 0 7 0 500K 0 3 0 1M 0 1 0 Blank Cannot be set A setting can be made but an error will result Notes The value set in BRR is given...

Page 371: ...ck SMR Setting n Clock CKS1 CKS0 0 0 0 0 w 2 1 w 2 0 1 2 16 1 0 3 64 1 1 Notes 1 w 2 clock in active medium speed high speed mode and sleep mode 2 w clock in subactive mode and subsleep mode In subact...

Page 372: ...5 SCI3 Module Standby Mode Control S32CKSTP Bit 5 controls setting and clearing of module standby mode for SCI3 S32CKSTP Description 0 SCI3 is set to module standby mode 1 SCI3 module standby mode is...

Page 373: ...itten to this bit Bit 3 TXD32 Pin Output Data Inversion Switch Bit 3 specifies whether or not TXD32 pin output data is to be inverted Bit 3 SCINV3 Description 0 TXD32 output data is not inverted initi...

Page 374: ...s determines the data transfer format and the character length Framing error FER parity error PER overrun error OER and break detection during reception Choice of internal or external clock as the clo...

Page 375: ...Multiprocessor Bit Parity Bit Stop Bit Length 0 0 0 0 0 8 bit data No No 1 bit 1 2 bits 1 0 Asynchronous mode Yes 1 bit 1 2 bits 1 0 0 7 bit data No 1 bit 1 2 bits 1 0 Yes 1 bit 1 2 bits 0 1 0 0 8 bit...

Page 376: ...to 1 at this time RXI is enabled and an interrupt is requested See figure 10 2 a The RXI interrupt routine reads the receive data transferred to RDR and clears bit RDRF to 0 Continuous reception can...

Page 377: ...ng and RXI Interrupt TDR next transmit data TSR transmission in progress TDRE 0 TXD32 pin TDR TSR transmission completed transfer TDRE 1 TXI request when TIE 1 TXD32 pin Figure 10 2 b TDRE Setting and...

Page 378: ...bit 1 bit Transmit receive data Parity bit Stop bit s 5 7 or 8 bits One transfer data unit character or frame 1 bit or none 1 or 2 bits Mark state 1 MSB LSB Figure 10 3 Data Format in Asynchronous Com...

Page 379: ...0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PE MP STOP 2 3 4 5 8 bit data Serial Data Transfer Format and Frame Length SMR STOP S 6 7 8 9 10 11 12 8 bit data S 7 bit data STOP STOP S STOP 7 bit data S STOP STOP 5...

Page 380: ...in figure 10 4 1 character 1 frame 0 D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Clock Serial data Figure 10 4 Phase Relationship between Output Clock and Transfer Data Asynchronous Mode 8 bit data parity 2 stop...

Page 381: ...tting bits CKE1 and CKE0 If clock output is selected for reception in synchronous mode the clock is output immediately after bits CKE1 CKE0 and RE are set to 1 Set the data transfer format in the seri...

Page 382: ...er SSR and check that bit TDRE is set to 1 then write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically After the TE bit is set to 1 on...

Page 383: ...when the stop bit has been sent starts transmission of the next frame If bit TDRE is set to 1 bit TEND in SSR bit is set to 1the mark state in which 1s are transmitted is established after the stop b...

Page 384: ...r processing A Read bits OER PER and FER in the serial status register SSR to determine if there is an error If a receive error has occurred execute receive error processing Read SSR and check that bi...

Page 385: ...y error processing If a receive error has occurred read bits OER PER and FER in SSR to identify the error and after carrying out the necessary error processing ensure that bits OER PER and FER are all...

Page 386: ...the receive data is stored in RDR If bit RIE is set to 1 in SCR3 an RXI interrupt is requested If the error checks identify a receive error bit OER PER or FER is set to 1 depending on the kind of erro...

Page 387: ...ERI request in response to framing error Figure 10 9 Example of Operation when Receiving in Asynchronous Mode 8 Bit Data Parity 1 Stop Bit 10 3 3 Operation in Synchronous Mode In synchronous mode SCI...

Page 388: ...with the LSB and ends with the MSB After output of the MSB the communication line retains the MSB state When receiving in synchronous mode SCI3 latches receive data at the rising edge of the serial c...

Page 389: ...TE to 0 in SCR3 No TDRE 1 Yes Continue data transmission No TEND 1 Yes Yes No Read the serial status register SSR and check that bit TDRE is set to 1 then write transmit data to the transmit data reg...

Page 390: ...ransfers data from TDR to TSR and starts transmission of the next frame If bit TDRE is set to 1 SCI3 sets bit TEND to 1 in SSR and after sending the MSB bit 7 retains the MSB state If bit TEIE in SCR3...

Page 391: ...serial status register SSR to determine if there is an error If an overrun error has occurred execute overrun error processing Read SSR and check that bit RDRF is set to 1 If it is read the receive da...

Page 392: ...or bit OER is set to 1 Bit RDRF remains set to 1 If bit RIE is set to 1 in SCR3 an ERI interrupt is requested See table 10 12 for the conditions for detecting a receive error and receive data processi...

Page 393: ...eared to 0 automatically Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR When the RDR data is read bit RDRF is cleared to 0 automatically When continuing data transm...

Page 394: ...on each receiver is assigned its own ID code The serial communication cycle consists of two cycles an ID transmission cycle in which the receiver is specified and a data transmission cycle in which th...

Page 395: ...munication Using Multiprocessor Format Sending Data H AA to Receiver A There is a choice of four data transfer formats If a multiprocessor format is specified the parity bit specification is invalid S...

Page 396: ...then set bit MPBT in SSR to 0 or 1 and write transmit data to the transmit data register TDR When data is written to TDR bit TDRE is cleared to 0 automatically When continuing data transmission be sur...

Page 397: ...SR bit is set to 1 the mark state in which 1s are transmitted is established after the stop bit has been sent If bit TEIE in SCR3 is set to 1 at this time a TEI request is made Figure 10 18 shows an e...

Page 398: ...rror processing Read SSR and check that bit RDRF is set to 1 If it is read the receive data in RDR and compare it with this receiver s own ID If the ID is not this receiver s set bit MPIE to 1 again W...

Page 399: ...ng Clear bits OER and FER to 0 in SSR Yes OER 1 Yes Yes FER 1 Break No No No Overrun error processing Framing error processing A Figure 10 19 Example of Multiprocessor Data Reception Flowchart cont Fi...

Page 400: ...o 1 again 1 frame Start bit Start bit Receive data ID2 Receive data Data2 MPB MPB Stop bit Stop bit Mark state idle state 1 frame 0 1 D0 D1 D7 1 1 1 1 0 a When data does not match this receiver s ID b...

Page 401: ...nitial value of bit TDRE in SSR is 1 Therefore if the transmit data empty interrupt request TXI is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR a TXI interrupt wi...

Page 402: ...mes 2 Operation when a number of receive errors occur simultaneously If a number of receive errors are detected simultaneously the status flags in SSR will be set to the states shown in table 10 14 If...

Page 403: ...he TXD32 pin functions as an I O port and 1 is output To detect a break clear bit TE to 0 after setting PCR 1 and PDR 0 When bit TE is cleared to 0 the transmission unit is initialized regardless of t...

Page 404: ...n equation 1 1 D 0 5 M 0 5 2N N L 0 5 F 100 Equation 1 where M Receive margin N Ratio of bit rate to clock N 16 D Clock duty D 0 5 to 1 0 L Frame length L 9 to 12 F Absolute value of clock frequency d...

Page 405: ...ation line RDRF RDR Frame 1 Frame 2 Frame 3 Data 1 Data 1 RDR read RDR read Data 1 is read at point A Data 2 Data 3 Data 2 A Data 2 is read at point B B Figure 10 22 Relation between RDR Read Timing a...

Page 406: ...SCK32 should be pulled up to the VCC level via a resistor or supplied with output from an external device b When an SCK32 function is switched from clock output to general input output When stopping d...

Page 407: ...y of the following conversion periods can be chosen 4 096 with a minimum modulation width of 4 2 048 with a minimum modulation width of 2 1 024 with a minimum modulation width of 1 512 with a minimum...

Page 408: ...igure 11 1 2 shows a block diagram of the 10 bit PWM of the H8 38124 Group Internal data bus PWDRLm PWDRUm PWCRm PWM waveform generator 2 4 8 Legend PWDRLm PWDRUm PWCRm PWM data register L PWM data re...

Page 409: ...2 Figure 11 1 2 Figure 11 1 1 Block Diagram of the 10 bit PWM H8 38124 Group 1 Channel Configuration 11 1 3 Pin Configuration Table 11 1 shows the output pin assigned to the 10 bit PWM Table 11 1 Pin...

Page 410: ...ote Implemented on H8 38124 Group only 11 2 Register Descriptions 11 2 1 PWM Control Register PWCRm Bit Initial value Read Write Note Implemented on H8 38124 Group only 7 1 6 1 5 1 4 1 3 1 0 PWCRm0 0...

Page 411: ...ect the clock supplied to the 10 bit PWM These bits are write only bits they are always read as 1 Bit 1 PWCRm1 Bit 0 PWCRm0 Description 0 0 The input clock is t 1 initial value The conversion period i...

Page 412: ...d to PWDRUm and the lower 8 bits to PWDRLm The value written to PWDRUm and PWDRLm gives the total high level width of one PWM waveform cycle When 10 bit data is written to PWDRUm and PWDRLm the regist...

Page 413: ...Group CKSTPR2 is an 8 bit read write register that performs module standby mode control for peripheral modules Only the bit relating to the PWM is described here For details of the other bits see the...

Page 414: ...veform generator updating the PWM waveform generation in synchronization with internal signals One conversion period consists of 4 pulses as shown in figure 11 2 The total of the high level pulse widt...

Page 415: ...ration modes are shown in table 11 3 Table 11 3 PWM Operation Modes Operation Mode Reset Active Sleep Watch Sub active Sub sleep Standby Module Standby PWCRm Reset Functions Functions Retained Retaine...

Page 416: ...Rev 6 00 08 04 page 386 of 628...

Page 417: ...The A D converter has the following features 10 bit resolution Eight input channels Conversion time approx 12 4 s per channel at 5 MHz operation 7 8 s at 8 MHz operation Built in sample and hold funct...

Page 418: ...bus AMR ADSR ADRRH ADRRL Control logic Com parator AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG AV AV CC SS Multiplexer Reference voltage IRRAD AVCC AVSS Legend AMR ADSR ADRR IRRAD A D mode register A D sta...

Page 419: ...t Analog input channel 3 Analog input 4 AN4 Input Analog input channel 4 Analog input 5 AN5 Input Analog input channel 5 Analog input 6 AN6 Input Analog input channel 6 Analog input 7 AN7 Input Analog...

Page 420: ...er 8 bits of the data are held in ADRRH and the lower 2 bits in ADRRL ADRRH and ADRRL can be read by the CPU at any time but the ADRRH and ADRRL values during A D conversion are not fixed After A D co...

Page 421: ...east 12 4 s Bit 6 External Trigger Select TRGE Bit 6 enables or disables the start of A D conversion by external trigger input Bit 6 TRGE Description 0 Disables start of A D conversion by external tri...

Page 422: ...write register for starting and stopping A D conversion A D conversion is started by writing 1 to the A D start flag ADSF or by input of the designated edge of the external trigger signal which also s...

Page 423: ...STPR1 is an 8 bit read write register that performs module standby mode control for peripheral modules Only the bit relating to the A D converter is described here For details of the other bits see th...

Page 424: ...the conversion time or input channel needs to be changed in the A D mode register AMR during A D conversion bit ADSF should first be cleared to 0 stopping the conversion operation in order to avoid ma...

Page 425: ...by means of bit IENAD in interrupt enable register 2 IENR2 For further details see section 3 3 Interrupts 12 5 Typical Use An example of how the A D converter can be used is given below using channel...

Page 426: ...on 1 Idle A D conversion 2 Idle Interrupt IRRAD IENAD ADSF Channel 1 AN 1 operation state ADRRH ADRRL Set Set Set Read conversion result Read conversion result A D conversion result 1 A D conversion r...

Page 427: ...ersion speed and input channel Perform A D conversion End Yes No Disable A D conversion end interrupt Start A D conversion ADSF 0 No Yes Read ADSR Read ADRRH ADRRL data Figure 12 4 Flow Chart of Proce...

Page 428: ...sion accuracy definitions are given below Resolution The number of A D converter digital output codes Quantization error The deviation inherent in the A D converter given by 1 2 LSB see figure 12 6 Of...

Page 429: ...put value Includes offset error full scale error quantization error and nonlinearity error 111 110 101 100 011 010 001 000 1 8 2 8 6 8 7 8 FS Quantization error Digital output Ideal A D conversion cha...

Page 430: ...for which the signal source impedance is 10 k or less This specification is provided to enable the A D converter s sample and hold circuit input capacitance to be charged within the sampling time if...

Page 431: ...00 08 04 page 401 of 628 A D converter equivalent circuit This LSI 20 pF Cin 15 pF 10 k Up to 10 k Low pass filter C to 0 1 F Sensor output impedance Sensor input Figure 12 8 Analog Input Circuit Exa...

Page 432: ...Rev 6 00 08 04 page 402 of 628...

Page 433: ...ccess to LCD RAM All four segment output pins can be used individually as port pins Common output pins not used because of the duty cycle can be used for common double buffering parallel connection Di...

Page 434: ...ming generator LCD RAM 16 bytes Internal data bus 32 bit shift register LCD drive power supply Segment driver Common data latch Common driver V1 V2 V3 VSS COM1 COM4 SEG32 SEG1 Legend LPCR LCD port con...

Page 435: ...al data bus Display timing generator LCD RAM 16 bytes 32 bit shift register LCD drive power supply Segment driver Common data latch Common driver Legend LPCR LCD port control register LCR LCD control...

Page 436: ...used in parallel with static or 1 2 duty LCD power supply pins V1 V2 V3 Used when a bypass capacitor is connected externally and when an external power supply circuit is used 13 1 4 Register Configur...

Page 437: ...ultiple pins to increase the common drive power when not all common pins are used because of the duty setting Bit 7 DTS1 Bit 6 DTS0 Bit 5 CMX Duty Cycle Common Drivers Notes 0 0 0 Static COM1 initial...

Page 438: ...Port Port Port Port Port SEG SEG 1 Port Port Port Port Port SEG SEG SEG 1 0 0 Port Port Port Port SEG SEG SEG SEG 1 Port Port Port SEG SEG SEG SEG SEG 1 0 Port Port SEG SEG SEG SEG SEG SEG 1 Port SEG...

Page 439: ...wer supply off when LCD display is not required in a power down mode or when an external power supply is used When the ACT bit is cleared to 0 or in standby mode the LCD drive power supply is turned o...

Page 440: ...s are not performed if one of the clocks from 2 to 256 is selected If LCD display is required in these modes w w 2 or w 4 must be selected as the operating clock Frame Frequency 2 Bit 3 CKS3 Bit 2 CKS...

Page 441: ...itching between the A waveform and B waveform and removal of split resistance Note that removal of split resistance control is only implemented on the H8 38124 Group Bit 7 A Waveform B Waveform Switch...

Page 442: ...nce is removed or connected Note that on products other than the H8 38124 Group these bits are reserved like bit 4 Bit 3 CDS3 Bit 2 CDS2 Bit 1 CDS1 Bit 0 CDS0 Description 0 0 0 0 initial value 1 Split...

Page 443: ...egister that performs module standby mode control for peripheral modules Only the bit relating to the LCD controller driver is described here For details of the other bits see the sections on the rele...

Page 444: ...nel display As the impedance of the built in power supply split resistance is large it may not be suitable for driving a large panel If the display lacks sharpness when using a large panel refer to se...

Page 445: ...ts SGS3 to SGS0 c Frame frequency selection The frame frequency can be selected by setting bits CKS3 to CKS0 The frame frequency should be selected in accordance with the LCD panel specification For t...

Page 446: ...gisters required for display data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM and display is started automatically when turned on Word or by...

Page 447: ...of 628 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 H F740 H F74F SEG31 SEG32 SEG32 SEG32 SEG31 SEG31 COM3 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 1...

Page 448: ...COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 Display space Space not used for display Figure 13 5 LCD RAM Map 1 2 Duty Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG...

Page 449: ...1 frame M Data COM1 COM2 COM3 SEGn V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame M Data COM1 COM2 SEGn V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame M Data COM1 SEGn V1 VSS V1 VSS b Wa...

Page 450: ...frame 1 frame 1 frame 1 frame 1 frame 1 frame b Waveform with 1 3 duty M Data COM3 SEGn COM1 V1 V2 V3 VSS COM2 V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS a Waveform with 1 4 duty M Data COM1 COM2 COM3 COM...

Page 451: ...will halt Since there is a possibility that a direct current will be applied to the LCD panel in this case it is essential to ensure that w w 2 or w 4 is selected In active medium speed mode the syst...

Page 452: ...ity is insufficient when VCC is used as the power supply the power supply impedance must be reduced This can be done by connecting bypass capacitors of around 0 1 to 0 3 F to pins V1 to V3 as shown in...

Page 453: ...ate is held for a specified period then active mode is automatically entered Figure 14 1 is a block diagram of the power on reset circuit and the low voltage detection circuit Note The voltage maintai...

Page 454: ...ll rise detection voltage Power supply drop detection voltage input pin Power supply rise detection voltage input pin Reference voltage input pin RES CK R PSS Vcc R S Q OVF Vreset Vref extU extD Vint...

Page 455: ...s The registers of the power on reset circuit and low voltage detection circuit are listed in table 14 2 Table 14 2 Register Descriptions Name Symbol R W Initial Value Address Low voltage detection co...

Page 456: ...voltage detection circuit used Bit 6 Reserved This bit is a read write enabled reserved bit Bit 5 Power Supply Drop LVDD Detection Level External Input Select VINTDSEL This bit is used to select the p...

Page 457: ...s triggered by LVDR are enabled or disabled Bit 2 LVDRE Description 0 LVDR resets disabled initial value 1 LVDR resets enabled Bit 1 Voltage Drop Interrupt Enable LVDDE This bit is used to control whe...

Page 458: ...age Detection Status Register LVDSR Bit 7 6 5 4 3 2 1 0 OVF VREFSEL LVDDF LVDUF Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Note These bits initialized by resets trigged b...

Page 459: ...n to Bit 1 LVD Power Supply Voltage Drop Flag LVDDF This bit indicates when a power supply voltage drop has been detected Bit 1 LVDDF Description 0 Clearing condition initial value When 0 is written a...

Page 460: ...T is H 00 14 2 4 Clock Stop Register 2 CKSTPR2 Bit 7 6 5 4 3 2 1 0 LVDCKSTP PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP Initial value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W CKSTPR2 is an 8 b...

Page 461: ...table operation of this LSI the power supply needs to rise to its full level and settles within the specified time The maximum time required for the power supply to rise and settle after power has bee...

Page 462: ...ause incorrect operation may occur When the power supply voltage falls below the Vreset voltage typ 2 3 V or 3 3 V the LVDR clears the LVDRES signal to 0 and resets the prescaler S The low voltage det...

Page 463: ...ow Vint D typ 3 7 V voltage the LVDI clears the LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1 If the LVDDE bit is 1 at this time an IRQ0 interrupt request is simultaneously generated In th...

Page 464: ...ower supply drop interrupt is generated if the extD input voltage drops below Vexd After a power supply drop interrupt is generated if the external power supply voltage rises and the extU input voltag...

Page 465: ...tion Usage Example Employing Pins Vref extD and extU Below is an explanation of the method for calculating the external resistor values when using the Vref extD and extU pins for input of reference an...

Page 466: ...et1 Vint D and Vint U Make sure to double check the maximum and minimum values for each value Error Calculation Table Resistance Value Error Vref V R1 k R2 k R3 k 5 Comparator Error V Vreset1 V Vint D...

Page 467: ...to 1 2 After waiting for LVDCNT overflow etc to ensure that the stabilization time tLVDON 150 s for the reference voltage and low voltage detection power supply has elapsed clear bits LVDDF and LVDUF...

Page 468: ...Rev 6 00 08 04 page 438 of 628...

Page 469: ...internal power supply voltage without using the internal power supply step down circuit 15 1 When Using Internal Power Supply Step Down Circuit Connect the external power supply to the VCC pin and con...

Page 470: ...gure 15 2 The external power supply is then input directly to the internal power supply The permissible range for the power supply voltage is 2 7 V to 3 6 V Operation cannot be guaranteed if a voltage...

Page 471: ...PP 0 3 to 13 0 V Input voltage Ports other than Port B and IRQAEC Vin 0 3 to VCC 0 3 V Port B AVin 0 3 to AVCC 0 3 V IRQAEC HVin 0 3 to 7 3 V Port 9 pin voltage VP9 0 3 to 7 3 V Operating temperature...

Page 472: ...ply Voltage and Oscillator Frequency Range 38 4 1 8 3 0 5 5 VCC V f W kHz All operating Note 2 When an oscillator is used for the subclock hold VCC at 2 2 V to 5 5 V from power on until the oscillatio...

Page 473: ...e figure in parentheses is the minimum operating frequency when an external clock is input When using an oscillator the minimum operating frequency is 15 625 kHz Active high speed mode Sleep high spee...

Page 474: ...V to 5 5 V Input high voltage RES WKP0 to WKP7 IRQ0 IRQ1 IRQ3 IRQ4 AEVL AEVH TMIC TMIF TMIG ADTRG SCK32 0 9 VCC VCC 0 3 Except the above RXD32 UD 0 7 VCC VCC 0 3 V VCC 4 0 V to 5 5 V 0 8 VCC VCC 0 3 E...

Page 475: ...0 3 0 2 VCC Except the above OSC1 0 3 0 2 VCC V VCC 4 0 V to 5 5 V 0 3 0 1 VCC Except the above X1 0 3 0 1 VCC V VCC 1 8 V to 5 5 V 0 3 0 3 VCC V VCC 4 0 V to 5 5 V P13 P14 P16 P17 P30 to P37 P40 to P...

Page 476: ...IOL 0 4 mA P30 to P37 1 5 VCC 4 0 V to 5 5 V IOL 10 mA 0 6 VCC 4 0 V to 5 5 V IOL 1 6 mA 0 5 IOL 0 4 mA P90 to P92 0 5 VCC 2 2 to 5 5 V IOL 25 mA 5 IOL 15 mA 0 5 IOL 10 mA 6 P93 to P95 0 5 IOL 10 mA I...

Page 477: ...50 0 2 15 0 1 PB0 to PB7 15 0 IOPE1 VCC 7 0 10 0 mA Active high speed mode VCC 5 V fOSC 10 MHz 3 4 Active mode current dissipation IOPE2 VCC 2 2 3 0 mA Active medium speed mode VCC 5 V fOSC 10 MHz os...

Page 478: ...port 3 and 9 2 0 mA VCC 4 0 V to 5 5 V Port 3 10 0 VCC 4 0 V to 5 5 V Allowable output low current per pin Output pins except port 9 0 5 P90 to P92 25 0 VCC 2 2 V to 5 5 V 5 15 0 10 0 P93 to P95 10 0...

Page 479: ...alted System clock oscillator crystal Subclock oscillator Pin X1 GND Subactive mode VCC Operates VCC Halted Subsleep mode VCC Only timers operate CPU stops VCC Halted Watch mode VCC Only time base ope...

Page 480: ...2 2 0 16 0 MHz VCC 4 5 V to 5 5 V 2 0 10 0 VCC 2 7 V to 5 5 V System clock oscillation frequency 2 0 4 0 Except the above OSC clock OSC cycle time tOSC OSC1 OSC2 62 5 500 1000 ns VCC 4 5 V to 5 5 V Fi...

Page 481: ...V to 5 5 V Figure 16 1 External clock rise time 10 VCC 2 7 V to 5 5 V 25 Except the above X1 55 0 ns tCPf OSC1 6 ns VCC 4 5 V to 5 5 V Figure 16 1 External clock fall time 10 VCC 2 7 V to 5 5 V 25 Ex...

Page 482: ...e specifications Ta 75 C Die including subactive mode unless otherwise indicated Values Item Symbol Min Typ Max Unit Test Conditions Reference Figure Asynchronous tscyc 4 tcyc or Figure 16 4 Input clo...

Page 483: ...ble Pins Min Typ Max Unit Test Condition Reference Figure Analog power supply voltage AVCC AVCC 1 8 5 5 V 1 Analog input voltage AVIN AN0 to AN7 0 3 AVCC 0 3 V AIOPE AVCC 1 5 mA AVCC 5 0 V Analog powe...

Page 484: ...D characteristics Table 16 6 LCD Characteristics VCC 1 8 V to 5 5 V AVCC 1 8 V to 5 5 V VSS AVSS 0 0 V Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Ta 75 C Die incl...

Page 485: ...to 7 3 V Port 9 pin voltage VP9 0 3 to 7 3 V Operating temperature Topr 20 to 75 2 regular specifications C 40 to 85 2 wide range specifications 75 products shipped as chips 3 C Storage temperature T...

Page 486: ...voltage and operating range are indicated by the shaded region in the figures Power Supply Voltage and Oscillator Frequency Range 38 4 2 7 3 6 VCC V f W kHz All operating 32 768 2 0 10 0 2 7 3 6 VCC...

Page 487: ...sing an oscillator the minimum operating frequency is 1 MHz Note 2 The figure in parentheses is the minimum operating frequency when an external clock is input When using an oscillator the minimum ope...

Page 488: ...Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Input high voltage VIH RES WKP0 to WKP7 IRQ0 IRQ1 IRQ3 IRQ4 AEVL AEVH TMIC TMIF TMIG ADTRG SCK32 0 9 VCC VCC 0 3 V RXD32 UD 0 8 VCC V...

Page 489: ...CC V P13 P14 P16 P17 P30 to P37 P40 to P43 P50 to P57 P60 to P67 P70 to P77 P80 to P87 PA0 to PA3 PB0 to PB7 0 3 0 2 VCC V VCC 1 0 V IOH 1 0 mA Output high voltage VOH P13 P14 P16 P17 P30 to P37 P40 t...

Page 490: ...o PB7 1 0 A VIN 0 5 V to AVCC 0 5 V Pull up MOS current Ip P13 P14 P16 P17 P30 to P37 P50 to P57 P60 to P67 30 180 A VCC 3 V VIN 0 V Input capacitance CIN All input pins except power supply and IRQAEC...

Page 491: ...C 4 MHz osc 128 3 4 Max guideline 1 1 typ 1 2 1 8 mA Active medium speed mode VCC 3 V fOSC 10 MHz osc 128 3 4 ISLEEP VCC 1 0 mA VCC 3 V fOSC 2 MHz 3 4 Max guideline 1 1 typ Sleep mode current dissipat...

Page 492: ...ssipation ISTBY VCC 0 3 A VCC 3 0 V Ta 25 C 32 kHz crystal oscillator not used 3 4 Reference value 1 0 5 0 A 32 kHz crystal oscillator not used 3 4 RAM data retaining voltage VRAM VCC 2 0 V IOL Output...

Page 493: ...ted System clock oscillator crystal Subclock oscillator Pin X1 GND Subactive mode VCC Operates VCC Halted Subsleep mode VCC Only on chip timers operate CPU stops VCC Halted Watch mode VCC Only time ba...

Page 494: ...0 500 1000 ns Figure 16 1 2 tcyc 2 128 tOSC System clock cycle time 128 s Subclock oscillation frequency fW X1 X2 32 768 or 38 4 kHz Watch clock W cycle time tW X1 X2 30 5 or 26 0 s Figure 16 1 Subclo...

Page 495: ...tcyc Figure 16 2 Input pin high width tIH IRQ0 IRQ1 IRQ3 IRQ4 IRQAEC WKP0 to WKP7 TMIC TMIF TMIG ADTRG 2 tcyc tsubcyc Figure 16 3 AEVL AEVH 0 5 tosc Input pin low width tIL IRQ0 IRQ1 IRQ3 IRQ4 IRQAEC...

Page 496: ...st Conditions Reference Figure Asynchronous tscyc 4 tcyc or Figure 16 4 Input clock cycle Synchronous 6 t subcyc Input clock pulse width tSCKW 0 4 0 6 tscyc Figure 16 4 Transmit data delay time synchr...

Page 497: ...log power supply current AISTOP1 AVCC 600 A 2 Reference value AISTOP2 AVCC 5 A 3 Analog input capacitance CAIN AN0 to AN7 15 0 pF Allowable signal source impedance RAIN 10 0 k Resolution data length 1...

Page 498: ...to 3 6 V 1 Common driver drop voltage VDC COM1 to COM4 0 3 V ID 2 A V1 2 7 V to 3 6 V 1 RLCD 0 5 3 0 9 0 M 3 LCD power supply split resistance 1 5 3 0 7 0 Between V1 and VSS 4 Liquid crystal display...

Page 499: ...g Wait time after SWE bit setting 1 x 1 s Wait time after PSU bit setting 1 y 50 s Wait time after P bit setting 1 4 z1 28 30 32 s 1 n 6 z2 198 200 202 s 7 n 1000 z3 8 10 12 s Additional programming W...

Page 500: ...ng z1 z2 should be changed as follows according to the value of the number of writes n Number of writes n 1 n 6 z1 30 s 7 n 1000 z2 200 s 6 Erase time maximum value tE max wait time after E bit settin...

Page 501: ...Port B AVin 0 3 to AVCC 0 3 V Port 9 pin voltage VP9 0 3 to VCC 0 3 V Operating temperature Topr 20 to 75 regular specifications C 40 to 85 wide range specifications C 75 products shipped as chips 2 S...

Page 502: ...rating range are indicated by the shaded region in the figures Power Supply Voltage and Oscillator Frequency Range 38 4 1 8 2 7 3 6 VCC V f W kHz All operating 32 768 2 0 4 0 10 0 2 7 1 8 3 6 VCC V fo...

Page 503: ...ng frequency is 1 MHz Note 2 The figure in parentheses is the minimum operating frequency when an external clock is input When using an oscillator the minimum operating frequency is 15 625 kHz Active...

Page 504: ...Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Input high voltage VIH RES WKP0 to WKP7 IRQ0 IRQ1 IRQ3 IRQ4 AEVL AEVH TMIC TMIF TMIG ADTRG SCK32 0 9 VCC VCC 0 3 V RXD32 UD 0 8 VCC VCC 0 3...

Page 505: ...17 P30 to P37 P40 to P43 P50 to P57 P60 to P67 P70 to P77 P80 to P87 PA0 to PA3 PB0 to PB7 0 3 0 2 VCC V Output high voltage VOH P13 P14 P16 P17 P30 to P37 P40 to P42 P50 to P57 P60 to P67 P70 to P77...

Page 506: ...A VIN 0 5 V to AVCC 0 5 V Pull up MOS current Ip P13 P14 P16 P17 P30 to P37 P50 to P57 P60 to P67 30 180 A VCC 3 V VIN 0 V Input capacitance CIN All input pins except power supply and IRQAEC 15 0 pF...

Page 507: ...de VCC 1 8 V fOSC 1 MHz osc 128 1 2 Max guideline 1 1 typ 0 1 mA Active medium speed mode VCC 3 V fOSC 2 MHz osc 128 1 2 Max guideline 1 1 typ 0 2 mA Active medium speed mode VCC 3 V fOSC 4 MHz osc 12...

Page 508: ...Reference value 4 4 A VCC 2 7 V LCD on 32 kHz crystal oscillator SUB w 8 1 2 Reference value 10 40 A VCC 2 7 V LCD on 32 kHz crystal oscillator SUB w 2 1 2 Subsleep mode current dissipation ISUBSP VCC...

Page 509: ...kHz crystal oscillator not used 1 2 Reference value 1 0 5 0 A 32 kHz crystal oscillator not used 1 2 RAM data retaining voltage VRAM VCC 1 5 V IOL Output pins except port 9 0 5 mA Allowable output low...

Page 510: ...IOPE2 Subclock oscillator Pin X1 GND Sleep mode VCC Only on chip timers operate VCC Halted Subactive mode VCC Operates VCC Halted System clock oscillator Subsleep mode VCC Only on chip timers operate...

Page 511: ...cycle time tOSC OSC1 OSC2 100 500 1000 ns VCC 2 7 V to 3 6 V Figure 16 1 2 250 500 1000 ns VCC 1 8 V to 3 6 V tcyc 2 128 tOSC System clock cycle time 128 s Subclock oscillation frequency fW X1 X2 32...

Page 512: ...3 6 V X1 55 0 ns tCPf OSC1 10 ns VCC 2 7 V to 3 6 V Figure 16 1 External clock fall time 25 ns VCC 1 8 V to 3 6 V X1 55 0 ns Pin RES low width tREL RES 10 tcyc Figure 16 2 Input pin high width tIH IRQ...

Page 513: ...st Conditions Reference Figure Asynchronous tscyc 4 tcyc or Figure 16 4 Input clock cycle Synchronous 6 t subcyc Input clock pulse width tSCKW 0 4 0 6 tscyc Figure 16 4 Transmit data delay time synchr...

Page 514: ...0 pF Allowable signal source impedance RAIN 10 0 k Resolution data length 10 bit Nonlinearity error 3 5 LSB AVCC 2 7 V to 3 6 V VCC 2 7 V to 3 6 V 5 5 LSB AVCC 2 0 V to 3 6 V VCC 2 0 V to 3 6 V 7 5 LS...

Page 515: ...S SEG1 to SEG32 0 6 V ID 2 A V1 2 7 V to 3 6 V 1 Common driver drop voltage VDC COM1 to COM4 0 3 V ID 2 A V1 2 7 V to 3 6 V 1 LCD power supply split resistance RLCD 1 5 3 0 7 0 M Between V1 and VSS Li...

Page 516: ...t B AVin 0 3 to AVCC 0 3 V Port 9 pin voltage VP9 0 3 to VCC 0 3 V Operating temperature Topr 20 to 75 2 regular specifications C 40 to 85 2 wide range temperature specifications Storage temperature T...

Page 517: ...cy Range System Clock Oscillator Selected 5 5 VCC V f W kHz All operating modes 32 768 2 7 2 0 16 0 2 7 5 5 VCC V fosc MHz Active high speed mode Sleep high speed mode Power Supply Voltage and Oscilla...

Page 518: ...lator Selected Subactive mode Subsleep mode except CPU Watch mode except CPU 16 384 8 192 4 096 2 7 5 5 VCC V SUB kHz 8 0 1 0 2 7 5 5 VCC V MHz Active high speed mode Sleep high speed mode except CPU...

Page 519: ...ator Selected Subactive mode Subsleep mode except CPU Watch mode except CPU 16 384 8 192 4 096 2 7 5 5 VCC V SUB kHz 1 0 0 35 2 7 5 5 VCC V MHz Active high speed mode Sleep high speed mode except CPU...

Page 520: ...ve high speed mode Sleep high speed mode 1000 500 2 7 5 5 AVCC V kHz Active medium speed mode Sleep medium speed mode Analog Power Supply Voltage and A D Converter Operating Range On Chip Oscillator S...

Page 521: ...EVL AEVH TMIC TMIF TMIG ADTRG SCK32 VCC 0 9 VCC 0 3 Other than above RXD32 UD VCC 0 7 VCC 0 3 V VCC 4 0 V to 5 5 V VCC 0 8 VCC 0 3 Other than above OSC1 VCC 0 8 VCC 0 3 V VCC 4 0 V to 5 5 V VCC 0 9 VC...

Page 522: ...0 3 V VCC 4 0 V to 5 5 V 0 3 VCC 0 2 Other than above OSC1 0 3 VCC 0 2 V VCC 4 0 V to 5 5 V 0 3 VCC 0 1 Other than above 0 3 VCC 0 3 V VCC 4 0 V to 5 5 V P13 P14 P17 P30 to P37 P40 to P43 P50 to P57 P...

Page 523: ...IOL 15 mA 1 0 VCC 4 0 V to 5 5 V IOL 10 mA 0 8 VCC 4 0 V to 5 5 V IOL 8 mA 1 0 IOL 5 mA 0 6 IOL 1 6 mA 0 5 IOL 0 4 mA IIL RES P43 P13 P14 P17 OSC1 X1 P30 to P37 P40 to P42 P50 to P57 P60 to P67 P70 t...

Page 524: ...peed mode VCC 2 7 V fOSC 2 MHz 1 3 4 Approx max value 1 1 Typ 1 0 2 3 4 Approx max value 1 1 Typ TBD Active high speed mode VCC 5 V fOSC 2 MHz 1 3 4 Approx max value 1 1 Typ 1 8 2 3 4 Approx max value...

Page 525: ...V fOSC 2 MHz OSC 128 1 3 4 Approx max value 1 1 Typ 0 5 2 3 4 Approx max value 1 1 Typ TBD Active medium speed mode VCC 5 V fOSC 2 MHz OSC 128 1 3 4 Approx max value 1 1 Typ 0 8 2 3 4 Approx max value...

Page 526: ...9 2 3 4 Approx max value 1 1 Typ TBD VCC 5 V fOSC 4 MHz 1 3 4 Approx max value 1 1 Typ 1 3 2 3 4 TBD TBD 1 3 4 2 2 5 0 VCC 5 V fOSC 10 MHz 2 3 4 ISUB VCC TBD A 1 3 4 Reference value Subactive mode cu...

Page 527: ...C 2 7 V Ta 25 C 32 kHz crystal resonator not used 1 3 4 Reference value Standby mode current consump tion 0 5 VCC 2 7 V Ta 25 C 32 kHz crystal resonator not used 2 3 4 Reference value 0 05 VCC 2 7 V T...

Page 528: ...o 5 5 V 8 0 Allowable output low current total IOL Output pins except ports 3 and 9 40 0 mA VCC 4 0 V to 5 5 V Port 3 80 0 VCC 4 0 V to 5 5 V Output pins except port 9 20 0 Port 9 80 0 IOH All output...

Page 529: ...k Pin X1 GND Subactive mode VCC Only CPU operates VCC Stops Subsleep mode VCC Only all on chip timers operate CPU stops VCC Stops Watch mode VCC Only clock time base operates CPU stops VCC Stops Syste...

Page 530: ...me tOSC OSC1 OSC2 62 5 500 ns Figure 16 1 500 1429 On chip oscillator selected tcyc 2 128 tOSC System clock cycle time 182 s Subclock oscillation frequency fW X1 X2 32 768 kHz Watch clock W cycle time...

Page 531: ...voltage and variation among production lots When designing systems make sure to give due consideration to the SPEC range Please see the Web site for this product for actual performance data Table 16 2...

Page 532: ...g power supply current AISTOP1 AVCC 600 A 2 Reference value AISTOP2 AVCC 5 0 A 3 Analog input capacitance CAIN AN0 to AN3 15 0 pF Allowable signal source impedance RAIN 10 0 k Resolution data length 1...

Page 533: ...voltage VDS SEG1 to SEG25 0 6 V ID 2 A V1 2 7 V to 5 5 V 1 Common driver step down voltage VDC COM1 to COM4 0 3 V ID 2 A V1 2 7 V to 5 5 V 1 LCD power supply split resistance RLCD 1 5 3 0 7 0 M Betwee...

Page 534: ...n Typ Max Unit Test Conditions Programming time 1 2 4 tP 7 200 ms 128 bytes Erase time 1 3 5 tE 100 1200 ms block Reprogramming count NWEC 1000 8 10000 9 times Data retain period tDRP 10 10 year Progr...

Page 535: ...ion time 4 Maximum programming time tP max tP max Wait time after P bit setting z maximum number of writes N 5 The maximum number of writes N should be set according to the actual set value of z1 z2 a...

Page 536: ...6 28 Power Supply Voltage Detection Circuit Characteristics 2 Using on chip reference voltage and ladder resistor VREFSEL VINTDSEL VINTUSEL 0 Rated Values Item Symbol Min Typ Max Unit Test Conditions...

Page 537: ...lues Item Symbol Min Typ Max Unit Test Condition extD extU interrupt detection level Vexd 0 80 1 20 1 60 V 0 3 VCC 0 3 or AVCC 0 3 whichever is lower V VCC 2 7 to 3 3 V extD extU pin input voltage 2 V...

Page 538: ...Vref3 0 1 V LVDSEL 0 Vref input voltage Vreset1 Vref3 2 0 89 2 77 V Vreset1 Reset detection voltage 2 Vreset2 1 2 76 Vref4 0 1 2 76 Vref4 2 76 Vref4 0 1 V LVDSEL 1 Vref input voltage Vreset2 Vref4 2...

Page 539: ...Note The VextD voltage must always be greater than the VextU voltage 16 8 8 Power On Reset Circuit Characteristics Table 16 32 Power On Reset Circuit Characteristics VCC 2 7 V to 5 5 V AVCC 2 7 V to...

Page 540: ...n Typ Max Unit Note Test Condition On chip oscillator overflow time tOVF 0 2 0 4 s Note When the on chip oscillator is selected the timer counts from 0 to 255 indicating the time remaining until an in...

Page 541: ...Rev 6 00 08 04 page 511 of 628 VIH VIL tIL IRQ0 IRQ1 IRQ3 IRQ4 TMIC TMIF TMIG ADTRG WKP0 to WKP7 IRQAEC AEVL AEVH tIH Figure 16 3 Input Timing tscyc tSCKW 32 SCK Figure 16 4 SCK3 Input Clock Timing...

Page 542: ...SCK TXD32 transmit data RXD32 receive data Note Output timing reference levels Output high Output low Load conditions are shown in figure 16 7 V 1 2Vcc 0 2 V V 0 8 V Figure 16 5 SCI3 Synchronous Mode...

Page 543: ...Condition 16 11 Resonator Equivalent Circuit CS CO Frequency MHz RS max CO max 4 100 16 pF 4 193 100 16 pF 10 30 16 pF Crystal Resonator Parameters RS OSC2 OSC1 LS Frequency MHz RS max CO max 2 18 3...

Page 544: ...2 Manufacturer s Publicly Released Values Frequency MHz RS max CO max 10 4 6 32 31 pF Figure 16 9 Resonator Equivalent Circuit 2 16 12 Usage Note The ZTAT F ZTAT and mask ROM versions satisfy the ele...

Page 545: ...g in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer xx 3 8 16 Immediate data 3 8 or 16 bits d 8 16 Displacement 8 or 16 bits aa 8 16 Absolute address 8 or 16 bi...

Page 546: ...B Rd16 1 Rd16 2 0 6 Rs8 Rd16 MOV B Rs aa 8 B Rs8 aa 8 2 0 4 MOV B Rs aa 16 B Rs8 aa 16 4 0 6 MOV W xx 16 Rd W xx 16 Rd 4 0 4 MOV W Rs Rd W Rs16 Rd16 2 0 2 MOV W Rs Rd W Rs16 Rd16 2 0 4 MOV W d 16 Rs...

Page 547: ...8 decimal adjust Rd8 2 3 2 SUB B Rs Rd B Rd8 Rs8 Rd8 2 2 SUB W Rs Rd W Rd16 Rs16 Rd16 2 1 2 SUBX B xx 8 Rd B Rd8 xx 8 C Rd8 2 2 2 SUBX B Rs Rd B Rd8 Rs8 C Rd8 2 2 2 SUBS W 1 Rd W Rd16 1 Rd16 2 2 SUBS...

Page 548: ...B Rd8 xx 8 Rd8 2 0 2 OR B Rs Rd B Rd8 Rs8 Rd8 2 0 2 XOR B xx 8 Rd B Rd8 xx 8 Rd8 2 0 2 XOR B Rs Rd B Rd8 Rs8 Rd8 2 0 2 NOT B Rd B Rd Rd 2 0 2 SHAL B Rd B 2 2 SHAR B Rd B 2 0 2 SHLL B Rd B 2 0 2 SHLR B...

Page 549: ...Rd16 0 4 8 BCLR xx 3 aa 8 B xx 3 of aa 8 0 4 8 BCLR Rn Rd B Rn8 of Rd8 0 2 2 BCLR Rn Rd B Rn8 of Rd16 0 4 8 BCLR Rn aa 8 B Rn8 of aa 8 0 4 8 BNOT xx 3 Rd B xx 3 of Rd8 2 2 xx 3 of Rd8 BNOT xx 3 Rd B x...

Page 550: ...x 3 Rd B C xx 3 of Rd16 4 8 BST xx 3 aa 8 B C xx 3 of aa 8 4 8 BIST xx 3 Rd B C xx 3 of Rd8 2 2 BIST xx 3 Rd B C xx 3 of Rd16 4 8 BIST xx 3 aa 8 B C xx 3 of aa 8 4 8 BAND xx 3 Rd B C xx 3 of Rd8 C 2 2...

Page 551: ...PC 2 2 4 BHI d 8 C Z 0 2 4 BLS d 8 C Z 1 2 4 BCC d 8 BHS d 8 C 0 2 4 BCS d 8 BLO d 8 C 1 2 4 BNE d 8 Z 0 2 4 BEQ d 8 Z 1 2 4 BVC d 8 V 0 2 4 BVS d 8 V 1 2 4 BPL d 8 N 0 2 4 BMI d 8 N 1 2 4 BGE d 8 N...

Page 552: ...R4L 1 R4L Until R4L 0 else next Notes 1 Set to 1 when there is a carry or borrow from bit 11 otherwise cleared to 0 2 If the result is zero the previous value of the flag is retained otherwise the fla...

Page 553: ...code map It shows the operation codes contained in the first byte of the instruction code bits 15 to 8 of the first instruction word Instruction when first bit of byte 2 bit 7 of first instruction wor...

Page 554: ...XL ROTL LDC BLS BTST ROTXR ROTR ORC OR BCC RTS XORC XOR BCS BSR BOR BIOR BXOR BIXOR BAND BIAND ANDC AND BNE RTE LDC BEQ NOT NEG BLD BILD BST BIST ADD SUB BVC BVS MOV INC DEC BPL JMP ADDS SUBS BMI EEPM...

Page 555: ...nd an on chip RAM is accessed BSET 0 FF00 From table A 4 I L 2 J K M N 0 From table A 3 SI 2 SL 2 Number of states required for execution 2 2 2 2 8 When instruction is fetched from on chip ROM branch...

Page 556: ...X ADDX B xx 8 Rd 1 ADDX B Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 ANDC ANDC xx 8 CCR 1 BAND BAND xx 3 Rd 1 BAND xx 3 Rd 2 1 BAND xx 3 aa 8 2 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8...

Page 557: ...aa 8 2 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 Rd 2 1 BIXOR xx 3 aa 8 2 1 BLD BLD xx 3 Rd 1 BLD xx 3 Rd 2 1 BLD xx 3 aa 8 2 1 BNOT BNOT xx 3 Rd 1 BNOT xx 3 Rd 2 2 BNOT xx 3 aa 8 2 2 BNOT Rn Rd 1 BNOT Rn Rd...

Page 558: ...2 JMP aa 16 2 2 JMP aa 8 2 1 2 JSR JSR Rn 2 1 JSR aa 16 2 1 2 JSR aa 8 2 1 1 LDC LDC xx 8 CCR 1 LDC Rs CCR 1 MOV MOV B xx 8 Rd 1 MOV B Rs Rd 1 MOV B Rs Rd 1 1 MOV B d 16 Rs Rd 2 1 MOV B Rs Rd 1 1 2 M...

Page 559: ...EG B Rd 1 NOP NOP 1 NOT NOT B Rd 1 OR OR B xx 8 Rd 1 OR B Rs Rd 1 ORC ORC xx 8 CCR 1 ROTL ROTL B Rd 1 ROTR ROTR B Rd 1 ROTXL ROTXL B Rd 1 ROTXR ROTXR B Rd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL B Rd...

Page 560: ...Address H F0 Bit Names Lower Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H 20 FLMCR1 SWE ESU PSU EV PV E P ROM H 21 FLMCR2 FLER H 22 FLPWCR PDWND H 23 EBR EB4 EB...

Page 561: ...4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 event counter H 8E ECPWDRH ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 H 8F ECPWDRL ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWD...

Page 562: ...E B2WI WDON BOWI WRST Watchdog H B3 TCW TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 timer H B4 TMC TMC7 TMC6 TMC5 _ _ TMC2 TMC1 TMC0 Timer C H B5 TCC TLC TCC7 TLC7 TCC6 TLC6 TCC5 TLC5 TCC4 TLC4 TCC3 TLC3...

Page 563: ...CA PMR3 AEVL AEVH TMOFH TMOFL UD H CB H CC PMR5 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 H CD PWCR2 PWCR22 PWCR21 PWCR20 10 bit PWM2 H CE PWDRU2 PWDRU21 PWDRU20 H CF PWDRL2 PWDRL27 PWDRL26 PWDRL25 PWDR...

Page 564: ...R76 PCR75 PCR74 PCR73 PCR72 PCR71 PCR70 H EB PCR8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 H EC PMR9 PIOFF PWM2 PWM1 H ED PCRA PCRA3 PCRA2 PCRA1 PCRA0 H EE PMRB IRQ1 H EF H F0 SYSCR1 SSBY STS2...

Page 565: ...1 1 1 0 0 1 1 0 1 0 1 Counts on external event TMIF rising falling edge Clock select L 1 1 1 1 0 0 1 1 0 1 0 1 Internal clock 32 Internal clock 16 Internal clock 4 Internal clock w 4 0 Don t care R W...

Page 566: ...etting condition When SWE 1 and ESU 1 Program Verify 0 Program verify mode cleared initial value 1 Transition to program verify mode Setting condition When SWE 1 Erase Verify 0 Erase verify mode clear...

Page 567: ...5 0 0 0 2 0 1 0 4 0 Flash memory error 3 0 FLPWCR Flash Memory Power Control Register H F022 Flash Memory Bit Initial value Read Write 7 PDWND 0 R W 6 0 5 0 0 0 2 0 1 0 4 0 Power down Disable 0 When t...

Page 568: ...4 0 R W Blocks 4 to 0 0 When a block of EB4 to EB0 is not selected initial value 1 When a block of EB4 to EB0 is selected 3 EB3 0 R W FENR Flash Memory Enable Register H F02B Flash Memory Bit Initial...

Page 569: ...ltage drop interrupt requests disabled initial value 1 Voltage drop interrupt requests enabled LVDR Enable 0 LVDR resets disabled initial value 1 LVDR resets enabled LVDR Detection Level Select 0 Rese...

Page 570: ...Vint D while the LVDUE bit in LVDCR is set to 1 and it rises above Vint U before dropping below Vreset1 LVD Power Supply Voltage Drop Flag 0 Clearing condition initial value When 0 is written after r...

Page 571: ...1 1 1 1 1 1 1 Bit Initial value R W 7 R W 6 R W 5 R W 4 R W 3 R W 2 R W 1 R W 0 R W Sets event counter PWM waveform conversion period ECPWDRH Event Counter PWM Data Register H H 8E AEC ECPWDRH7 ECPWDR...

Page 572: ...H 90 System Control Bit Initial value Read Write 7 WKEGS7 0 R W 6 WKEGS6 0 R W 5 WKEGS5 0 R W 0 WKEGS0 0 R W 2 WKEGS2 0 R W 1 WKEGS1 0 R W 4 WKEGS4 0 R W WKPn Edge Selected 0 WKPn pin falling edge de...

Page 573: ...CINV2 0 R W 1 W 4 W RXD32 Pin Input Data Inversion Switch 0 RXD32 input data is not inverted 1 RXD32 input data is inverted TXD32 Pin Output Data Inversion Switch 0 TXD32 output data is not inverted 1...

Page 574: ...Select Bit 2 AIEGS0 0 1 0 1 Bit 3 AIEGS1 0 0 1 1 Falling edge on IRQAEC pin is sensed Rising edge on IRQAEC pin is sensed Both edges on IRQAEC pin are sensed Use prohibited Description AEC Edge Selec...

Page 575: ...H1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0 0 R W Event Counter PWM Clock Select Bit 2 PWCK1 0 0 1 1 Bit 3 PWCK2 0 0 0 0 1 1 2 4 8 16 32 64 Description Don t care Bit 1 PWCK0 0 1 0 1 0 1 AEC Clock Select L...

Page 576: ...d and count up function is enabled Count up Enable L 0 ECL event clock input is disabled ECL value is held 1 ECL event clock input is enabled Count up Enable H 0 ECH event clock input is disabled ECH...

Page 577: ...ECH3 0 R Note ECH and ECL can also be used as the upper and lower halves respectively of a 16 bit timer counter EC ECL Event Counter L H 97 AEC Bit Initial value Read Write 7 ECL7 0 R 6 ECL6 0 R 5 EC...

Page 578: ...ck Multiprocessor Mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity 1 Odd parit...

Page 579: ...page 549 of 628 BRR Bit Rate Register H A9 SCI3 Bit Initial value Read Write 7 BRR7 1 R W 6 BRR6 1 R W 5 BRR5 1 R W 4 BRR4 1 R W 3 BRR3 1 R W 0 BRR0 1 R W 2 BRR2 1 R W 1 BRR1 1 R W Serial transmit re...

Page 580: ...t to 1 is received Transmit Enable 0 Transmit operation disabled TXD32 pin is I O port 1 Transmit operation enabled TXD32 pin is transmit data pin Receive Enable 0 Receive operation disabled RXD32 pin...

Page 581: ...4 page 551 of 628 TDR Transmit Data Register H AB SCI3 Bit Initial value Read Write 7 TDR7 1 R W 6 TDR6 1 R W 5 TDR5 1 R W 4 TDR4 1 R W 3 TDR3 1 R W 0 TDR0 1 R W 2 TDR2 1 R W 1 TDR1 1 R W Data for tra...

Page 582: ...After reading PER 1 cleared by writing 0 to PER 1 A parity error has occurred during reception Setting condition Framing Error 0 Reception in progress or completed normally Clearing condition After r...

Page 583: ...0 Timer A Bit Initial value Read Write 7 W 6 W 5 W 0 TMA0 0 R W 2 TMA2 0 R W 1 TMA1 0 R W Internal Clock Select TMA3 TMA2 0 PSS PSS PSS PSS 0 4 1 TMA1 0 1 TMA0 0 0 1 1 PSS PSS PSS PSS 1 0 1 0 0 1 1 1...

Page 584: ...Rev 6 00 08 04 page 554 of 628 TCA Timer Counter A H B1 Timer A Bit Initial value Read Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 0 TCA0 0 R 2 TCA2 0 R 1 TCA1 0 R Count value...

Page 585: ...and WDON while TCSRWE 1 1 Watchdog timer operation is enabled Setting condition 0 is written in B2WI and 1 is written in WDON while TCSRWE 1 Bit 0 Write Inhibit 0 Bit 0 is write enabled 1 Bit 0 is wri...

Page 586: ...TMC2 0 R W 1 TMC1 0 R W 4 1 Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock 8192 Internal clock 2048 Internal clock 512 Internal clock 64 Internal clock 16 Internal clock 4 Internal clock W 4...

Page 587: ...s returned 7 TCC7 0 R 6 TCC6 0 R 5 TCC5 0 R 3 TCC3 0 R 0 TCC0 0 R 2 TCC2 0 R 1 TCC1 0 R 4 TCC4 0 R Count value TLC Timer Load Register C H B5 Timer C Bit Initial value Read Write Note TLC is allocated...

Page 588: ...clock 16 Internal clock 4 Internal clock w 4 Counting on external event TMIF rising falling edge Toggle Output Level L 0 Low level 1 High level Toggle Output Level H 0 Low level 1 High level 3 TOLL 0...

Page 589: ...leared by writing 0 to CMFL 1 Setting condition Set when the TCFL value matches the OCRFL value Timer Overflow Flag L 0 Clearing condition After reading OVFL 1 cleared by writing 0 to OVFL 1 Setting c...

Page 590: ...t Initial value Read Write 7 TCFL7 0 R W 6 TCFL6 0 R W 5 TCFL5 0 R W 4 TCFL4 0 R W 3 TCFL3 0 R W 0 TCFL0 0 R W 2 TCFL2 0 R W 1 TCFL1 0 R W Count value Note TCFH and TCFL can also be used as the upper...

Page 591: ...F Bit Initial value Read Write 7 OCRFL7 1 R W 6 OCRFL6 1 R W 5 OCRFL5 1 R W 4 OCRFL4 1 R W 3 OCRFL3 1 R W 0 OCRFL0 1 R W 2 OCRFL2 1 R W 1 OCRFL1 1 R W Note OCRFH and OCRFL can also be used as the upp...

Page 592: ...t Capture Interrupt Edge Select 0 Interrupt generated on rising edge of input capture input signal 1 Interrupt generated on falling edge of input capture input signal Timer Overflow Interrupt Enable 0...

Page 593: ...F3 0 R 0 ICRGF0 0 R 2 ICRGF2 0 R 1 ICRGF1 0 R 4 ICRGF4 0 R Stores TCG value at falling edge of input capture signal ICRGR Input Capture Register GR H BE Timer G Bit Initial value Read Write 7 ICRGR7 0...

Page 594: ...er Select 3 SGS3 0 R W Port Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG SEG SEG SEG SEG SEG SEG SEG Port Port Port Port Port Port Port SEG...

Page 595: ...l Frame Frequency Select Operating Clock Bit 1 Bit 2 Bit 3 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 Bit 1 CKS1 CKS2 CKS3 CKS0 w w 2 w 4 2 4 8 16 32 64 128 256 Di...

Page 596: ...stance Control CDS3 Split resistance condition Other than the above 0 CDS2 1 CDS1 1 CDS0 1 Split resistance removed Split resistance connected Note The removal of split resistance control is only impl...

Page 597: ...by external trigger 1 Enables start of A D conversion by rising or falling edge of external trigger at pin ADTRG 5 1 4 AN5 AN6 AN 1 1 Do not specify this combination 7 1 0 0 1 1 0 1 AN0 AN1 AN2 AN3 Cl...

Page 598: ...defined R 1 ADR3 Undefined R 4 ADR6 Undefined R A D conversion result Bit Initial value Read Write ADRRL 7 ADR1 Undefined R 6 ADR0 Undefined R 5 3 0 2 1 4 A D conversion result ADSR A D Start Register...

Page 599: ...W 3 TMIG 0 R W 0 W 2 W 1 1 4 IRQ4 0 R W P13 TMIG Pin Function Switch 0 Functions as P13 I O pin 1 Functions as TMIG input pin P14 IRQ4 ADTRG Pin Function Switch 0 Functions as P14 I O pin 1 Functions...

Page 600: ...6 1 5 POF1 0 R W 4 1 3 1 0 IRQ0 0 R W 2 WDCKS 0 R W 1 NCS 0 R W P43 IRQ0 Pin Function Switch 0 Functions as P43 I O pin 1 Functions as IRQ0 input pin TMIG Noise Canceller Select 0 Noise cancellation...

Page 601: ...ch 0 Functions as P32 I O pin 1 Functions as TMOFH output pin P31 TMOFL Pin Function Switch 0 Functions as P31 I O pin 1 Functions as TMOFL output pin P30 UD Pin Function Switch 0 Functions as P30 I O...

Page 602: ...conversion period is 512 with a minimum modulation width of 1 2 The input clock is 2 t 1 2 The conversion period is 1 024 with a minimum modulation width of 1 The input clock is 4 t 1 4 The conversio...

Page 603: ...4 1 3 1 2 1 1 0 W 0 PWDRU21 PWDRU20 0 W Upper 2 bits of PWM2 waveform generation data PWDRL2 PWM2 Data Register L H CF 10 Bit PWM Lower 8 bits of PWM2 waveform generation data Bit Initial value Read W...

Page 604: ...ion width of 1 2 The input clock is 2 t 1 2 The conversion period is 1 024 with a minimum modulation width of 1 1 The input clock is 4 t 1 4 The conversion period is 2 048 with a minimum modulation wi...

Page 605: ...W 2 0 W 1 0 W Lower 8 bits of data for generating PWM1 waveform PWDRL15 PWDRL14 PWDRL13 PWDRL10 PWDRL12 PWDRL11 PWDRL16 PWDRL17 PDR1 Port Data Register 1 H D4 I O Ports Bit Initial value Read Write 7...

Page 606: ...W 5 P5 0 R W 4 P5 0 R W 3 P5 0 R W 0 P5 0 R W 2 P5 0 R W 1 P5 0 R W 3 0 2 1 4 5 6 7 Data for port 5 pins PDR6 Port Data Register 6 H D9 I O Ports Bit Initial value Read Write 7 P6 0 R W 6 P6 0 R W 5 P...

Page 607: ...DC I O Ports Bit Initial value Read Write 7 1 6 1 5 P95 1 R W 4 P94 1 R W 3 P93 1 R W 0 P90 1 R W 2 P92 1 R W 1 P91 1 R W Data for port 9 pins PDRA Port Data Register A H DD I O Ports Bit Initial val...

Page 608: ...ol Note When the PCR1 specification is 0 Input port specification Note PUCR16 is not equipped with H8 38124 Group PUCR3 Port Pull Up Control Register 3 H E1 I O Ports Bit Initial value Read Write 7 PU...

Page 609: ...CR6 Port Pull Up Control Register 6 H E3 I O Ports Bit Initial value Read Write 7 PUCR6 0 R W 6 PUCR6 0 R W 5 PUCR6 0 R W 4 PUCR6 0 R W 3 PUCR6 0 R W 0 PUCR6 0 R W 2 PUCR6 0 R W 1 PUCR6 0 R W 3 0 2 1...

Page 610: ...put pin 2 3 4 5 6 7 1 0 PCR4 Port Control Register 4 H E7 I O Ports Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 1 0 PCR4 0 W 2 PCR4 0 W 1 PCR4 0 W Port 4 Input Output Select 0 Input pin 1 Output pi...

Page 611: ...2 1 PCR7 Port Control Register 7 H EA I O Ports Bit Initial value Read Write 7 PCR7 0 W 6 PCR7 0 W 5 PCR7 0 W 4 PCR7 0 W 3 PCR7 0 W 0 PCR7 0 W 2 PCR7 0 W 1 PCR7 0 W Port 7 Input Output Select 0 Input...

Page 612: ...nction Switch Functions as P91 output pin Functions as PWM2 output pin 0 1 P92 to P90 Step up Circuit Control Large current port step up circuit is turned on Large current port step up circuit is turn...

Page 613: ...4 1 3 PCRA 0 W 0 PCRA 0 W 2 PCRA 0 W 1 PCRA 0 W 0 1 2 3 Port A Input Output Select 0 Input pin 1 Output pin PMRB Port Mode Register B H EE I O Ports Bit Initial value Read Write 7 1 6 1 5 1 4 1 3 IRQ...

Page 614: ...e medium speed Mode Clock Select osc 16 osc 32 0 1 0 0 1 1 osc 64 osc 128 1 1 0 0 1 0 1 Wait time 4 096 states 1 Wait time 2 states 1 Wait time 8 states 1 Wait time 16 states 1 Wait time 8 192 states...

Page 615: ...ode a direct transition is made to active medium speed mode if SSBY 0 MSON 1 and LSON 0 or to subactive mode if SSBY 1 TMA3 1 and LSON 1 When a SLEEP instruction is executed in active medium speed mod...

Page 616: ...pin input is detected Rising edge of IRQ0 pin input is detected 1 IRQ1 Edge Select 0 Falling edge of IRQ1 TMIC pin input is detected Rising edge of IRQ1 TMIC pin input is detected 1 IRQ3 Edge Select...

Page 617: ...ables IRQAEC interrupt requests 1 IRQ4 and IRQ3 Interrupt Enable 0 Disables IRQ4 and IRQ3 interrupt requests Enables IRQ4 and IRQ3 interrupt requests 1 Timer A Interrupt Enable 0 Disables timer A inte...

Page 618: ...mer FL interrupt requests 1 Enables timer FL interrupt requests Timer FH Interrupt Enable 0 Disables timer FH interrupt requests 1 Enables timer FH interrupt requests Timer C Interrupt Enable 0 Disabl...

Page 619: ...W 6 0 R 5 0 R W 0 0 R W 2 IRQAECF R 1 OSCF R 4 0 R W OSC Flag 0 Operation using system clock oscillator on chip oscillator stopped 1 Operation using on chip oscillator system clock oscillator stopped...

Page 620: ...rupt input and the designated signal edge is input IRQ4 and IRQ3 Interrupt Request Flags 0 Clearing condition When IRRIm 1 it is cleared by writting 0 m 4 or 3 1 Setting condition When pin IRQm is des...

Page 621: ...hen counter FH and output compare register FH match in 8 bit timer mode or when 16 bit counters FL and FH and output compare registers FL and FH match in 16 bit timer mode Timer FL Interrupt Request F...

Page 622: ...nly Bit Initial value Read Write 7 1 6 1 5 1 3 CKS3 1 R W 0 CKS0 1 R W 2 CKS2 1 R W 1 CKS1 1 R W 4 1 Internal Clock Select CDS3 Clock source 1 CDS2 0 CDS1 0 CDS0 0 64 1 0 0 1 128 1 0 1 0 256 1 0 1 1 5...

Page 623: ...IWPF5 0 R W 3 IWPF3 0 R W 0 IWPF0 0 R W 2 IWPF2 0 R W 1 IWPF1 0 R W 4 IWPF4 0 R W 0 Clearing condition When IWPFn 1 it is cleared by writing 0 n 7 to 0 Note All bits can only be written with 0 for fla...

Page 624: ...ed 1 A D Converter Module Standby Mode Control 0 A D converter is set to module standby mode A D converter module standby mode is cleared 1 0 Timer A is set to module standby mode Timer A module stand...

Page 625: ...et to module standby mode LVD module standby mode is cleared Note Control using the LVDCKST bit is implemented on the H8 38124 Group only 1 Asynchronous Event Counter Module Standby Mode Control 0 Asy...

Page 626: ...VCC VCC PUCR1n PMR1n PDR1n PCR1n Internal data bus SBY low level during reset and in standby mode VSS IRQm PDR1 PCR1 PMR1 PUCR1 n 7 and 4 m 4 and 3 Port data register 1 Port control register 1 Port m...

Page 627: ...and in standby mode VSS PUCR16 PMR16 PDR16 PCR16 Internal data bus P16 PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 Figure C 1...

Page 628: ...C SBY VSS PUCR13 PMR13 PDR13 PCR13 Timer G module TMIG Internal data bus P13 PDR1 PCR1 PMR1 PUCR1 Port data register 1 Port control register 1 Port mode register 1 Port pull up control register 1 Figu...

Page 629: ...C VCC PUCR3n PMR3n PDR3n PCR3n AEC module Internal data bus SBY VSS AEVH P36 AEVL P37 PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port pull up control regist...

Page 630: ...628 P35 VCC VCC PUCR35 PMR25 PDR35 PCR35 SBY VSS Internal data bus PDR3 PCR3 PUCR3 PMR2 Port data register 3 Port control register 3 Port pull up control register 3 Port mode register 2 Figure C 2 b P...

Page 631: ...v 6 00 08 04 page 601 of 628 P3n PDR3n PUCR3n PCR3n SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 n 4 and 3 Internal data bus VCC VCC Figure C 2 c Port 3 Block Diagram Pins P34 and P3...

Page 632: ...3n Internal data bus PMR3n PDR3n PCR3n SBY VSS PDR3 Port data register 3 PCR3 Port control register 3 PMR3 Port mode register 3 PUCR3 Port pull up control register 3 n 2 and 1 TMOFH P32 TMOFL P31 Figu...

Page 633: ...CC VSS PUCR30 PDR30 PCR30 UD SBY Internal data bus PDR3 PCR3 PMR3 PUCR3 Port data register 3 Port control register 3 Port mode register 3 Port pull up control register 3 P30 Timer C module PMR30 Figur...

Page 634: ...Rev 6 00 08 04 page 604 of 628 C 3 Block Diagrams of Port 4 P43 PMR20 Internal data bus IRQ0 PMR2 Port mode register 2 Figure C 3 a Port 4 Block Diagram Pin P43...

Page 635: ...v 6 00 08 04 page 605 of 628 P42 SCI3 module Internal data bus PDR42 SCINV3 PCR42 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 TXD32 VCC SPC32 Figure C 3 b Port 4 Block Diagram Pin P...

Page 636: ...v 6 00 08 04 page 606 of 628 P41 VCC SCI3 module PDR41 PCR41 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 RE32 RXD32 Internal data bus SCINV2 Figure C 3 c Port 4 Block Diagram Pin P4...

Page 637: ...08 04 page 607 of 628 P40 VCC SCI3 module PDR40 PCR40 SBY VSS PDR4 Port data register 4 PCR4 Port control register 4 SCKIE32 SCKOE32 SCKO32 Internal data bus SCKI32 Figure C 3 d Port 4 Block Diagram...

Page 638: ...PUCR5n Internal data bus PMR5n PDR5n PCR5n SBY VSS WKPn PDR5 Port data register 5 PCR5 Port control register 5 PMR5 Port mode register 5 PUCR5 Port pull up control register 5 n 7 to 0 Note The value...

Page 639: ...f 628 C 5 Block Diagram of Port 6 P6n VCC VCC PUCR6n PDR6n Internal data bus PCR6n SBY VSS PDR6 Port data register 6 PCR6 Port control register 6 PUCR6 Port pull up control register 6 n 7 to 0 Figure...

Page 640: ...Rev 6 00 08 04 page 610 of 628 C 6 Block Diagram of Port 7 P7n VCC PDR7n Internal data bus PCR7n SBY VSS PDR7 Port data register 7 PCR7 Port control register 7 n 7 to 0 Figure C 6 Port 7 Block Diagram...

Page 641: ...Rev 6 00 08 04 page 611 of 628 C 7 Block Diagram of Port 8 P8n VCC PDR8n Internal data bus PCR8n SBY VSS PDR8 PCR8 n 7 to 0 Port data register 8 Port control register 8 Figure C 7 Port 8 Block Diagram...

Page 642: ...PDR9n PMR9n SBY VSS PDR9 n 1 and 0 Port data register 9 PWM module PWMn 1 Internal data bus Figure C 8 a Port 9 Block Diagram Pins P91 and P90 P9n PDR9n SBY VSS PDR9 n 5 to 2 Port data register 9 Inte...

Page 643: ...Rev 6 00 08 04 page 613 of 628 C 9 Block Diagram of Port A PAn VCC PDRAn Internal data bus PCRAn SBY VSS PDRA Port data register A PCRA Port control register A n 3 to 0 Figure C 9 Port A Block Diagram...

Page 644: ...Rev 6 00 08 04 page 614 of 628 C 10 Block Diagram of Port B PBn Internal data bus AMR3 to AMR0 A D module VIN n 7 to 0 DEC Figure C 10 Port B Block Diagram...

Page 645: ...nctions Functions P67 to P60 High impedance Retained Retained High impedance 1 Retained Functions Functions P77 to P70 High impedance Retained Retained High impedance Retained Functions Functions P87...

Page 646: ...FP 80B HD64738024WI HD64738024W 80 pin TQFP TFP 80C HD64F38024H HD64F38024H 80 pin QFP FP 80A F ZTAT versions Regular specifications HD64F38024RH HD64F38024H HD64F38024F HD64F38024F 80 pin QFP FP 80B...

Page 647: ...A Wide range specifications HD64338020E HD64338020 F 80 pin QFP FP 80B HD64338020WI HD64338020 W 80 pin TQFP TFP 80C H8 38024S HD64338024SH HD64338024 H 80 pin QFP FP 80A H8 38024S Group Mask ROM vers...

Page 648: ...Wide range specifications HD64F38124WW F38124W 80 pin TQFP TFP 80C HD64338124H 38124 H 80 pin QFP FP 80A Mask ROM versions Regular specifications HD64338124W 38124 80 pin TQFP TFP 80C HD64338124HW 38...

Page 649: ...are shown in figures F 1 F 2 and F 3 below Package Code JEDEC JEITA Mass reference value FP 80A Conforms 1 2 g Dimension including the plating thickness Base material dimension 60 0 8 0 10 0 12 M 17...

Page 650: ...80B 1 7 g Dimension including the plating thickness Base material dimension 0 15 M 0 10 0 37 0 08 0 17 0 05 3 10 Max 1 2 0 2 24 8 0 4 20 64 41 40 25 24 1 80 65 18 8 0 4 14 0 15 0 8 2 70 2 4 0 20 0 10...

Page 651: ...FP 80C Conforms 0 4 g Dimension including the plating thickness Base material dimension 0 10 M 0 10 0 5 0 1 0 8 1 20 Max 14 0 0 2 0 5 12 14 0 0 2 60 41 1 20 80 61 21 40 0 17 0 05 1 0 0 22 0 05 0 10 0...

Page 652: ...628 7 0 7 0 0 15 4 0 20 C A 0 20 C B A B 0 575 0 575 1 20 Max 0 2 C 0 10 C C 0 08 C M A B 85 0 35 0 05 1 3 7 5 9 2 6 4 8 10 A C E G J B D F H 0 65 0 65 K Flatness of land portion Unit mm Figure F 4 T...

Page 653: ...of the HCD64338024S HCD64338023S HCD64338022S HCD64338021S and HCD64338020S are shown in figure G 3 X direction 3 99 0 05 Y direction 3 99 0 05 Maximum plain X direction 3 99 0 25 Y direction 3 99 0...

Page 654: ...irection 2 91 0 05 Y direction 2 91 0 05 Maximum plain X direction 2 91 0 25 Y direction 2 91 0 25 0 28 0 02 Max 0 03 Unit mm Figure G 3 Chip Sectional Figure of the HCD64338024S HCD64338023S HCD64338...

Page 655: ...he bonding pads for the HCD64338024 HCD64338023 HCD64338022 HCD64338021 HCD64338020 HCD64F38024 HCD64F38024R HCD64338024S HCD64338023S HCD64338022S HCD64338021S and HCD64338020S is shown in figure H 1...

Page 656: ...figure I 2 The specifications of the chip tray for the HCD64338024S HCD64338023S HCD64338022S HCD64338021S and HCD64338020S are shown in figure I 3 Chip direction Chip Type name Chip tray name DAINIP...

Page 657: ...ray name DAINIPPON INK CHEMICALS INC Type CT015 Carved code TCT45 060P X X cross section Unit mm 0 6 0 1 6 2 0 1 6 9 0 1 4 0 0 1 6 2 0 1 6 9 0 1 X X 4 24 3 84 51 51 4 5 0 05 1 8 0 1 4 5 0 05 Figure I...

Page 658: ...CHEMICALS INC Type CT022 Carved code TCT036036 060 X X cross section Unit mm 0 6 0 1 4 48 0 1 5 34 0 1 4 0 0 1 4 48 0 1 5 34 0 1 X X 2 91 2 91 51 51 3 6 0 05 3 6 0 05 1 8 0 1 Figure I 3 Specifications...

Page 659: ...Group Publication Date 1st Edition November 2000 Rev 6 00 August 27 2004 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation Information Department Rene...

Page 660: ...cher Str 3 D 85622 Feldkirchen Germany Tel 49 89 380 70 0 Fax 49 89 929 30 11 Renesas Technology Hong Kong Ltd 7 F North Tower World Finance Centre Harbour City Canton Road Hong Kong Tel 852 2265 6688...

Page 661: ...H8 38024 H8 38024S H8 38024F ZTAT H8 38124 Group Hardware Manual...

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