Renesas H8/38024 Series, Hardware Manual

Page: 12 / 661

Rev. 6.00, 08/04, page xii of xxx
Item Page Revisions (See Manual for Details)
9.6.2 Register
Descriptions 297 Timer Mode Register (TMW)
Bits 3 to 0—Clock Select (CKS3 to CKS0)
Bit table amended
Bit 3
CKS3 Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0
Description
0 X X X Watchdog on-chip oscillator
9.7.2 Register
Configurations 309 Event Counter Control/Status Register (ECCSR)
Description amended
• Bit 7—Control Overflow H (OVH)
• Bit 6—Counter Overflow L (OVL)
9.7.3 Operation
Figure 9.22 Event
Counter Operation
Waveform
316 Event Counter PWM Operation
Figure 9.22 amended
Ndr: Value of ECPWDRH and ECPWDRL Fixed low when Ndr
= H’FFFF
14.1 Overview 423 Note
*
added
Note: * The voltage maintained in standby mode is the same as
the RAM data retaining voltage (VRAM). See section 16.8.2,
DC Characteristics, for information on retaining voltage.
14.2.1 Low-Voltage
Detection Control
Register (LVDCR)
Table 14.3 LVDCR
Settings and Function
Register Selections
428 Note added
Note: Setting values marked with an asterisk (
*
) are invalid.
14.2.2 Low-Voltage
Detection Status
Register (LVDSR) 428 Note amended
Note:
*
These bits initialized by resets trigged by LVDR.
14.3.2 Low-Voltage
Detection Circuit
LVDR (Reset by Low
Voltage Detect) Circuit:
432 Description amended
To operate the LVDR, set the LVDE bit in LVDCR to 1, wait for
150
µ
s (t
LVDON
) until the reference voltage and the low-voltage-
detection power supply have stabilized, based on overflow of
LVDNT, etc., then set the LVDRE bit in LVDCR to 1.
LVDI (Interrupt by Low
Voltage Detect) Circuit: 433 Description amended
To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for
150
µ
s (t
LVDON
) until the reference voltage and the low-voltage-
detection power supply have stabilized, based on overflow of
LVDNT, etc., then set the LVDDE and LVDUE bits in LVDCR to
1.