Renesas H8/38024 Series, Hardware Manual

Page: 10 / 661

Rev. 6.00, 08/04, page x of xxx
Item Page Revisions (See Manual for Details)
4.1.1 Block Diagram
Figure 4.2 Block
Diagram of Clock Pulse
Generators (H8/38124
Group)
102 Figure 4.2 amended
(Before) Internal reset signal
→
(After) Internal reset signal
(other than watchdog timer or low-voltage detect circuit reset)
105 Table 4.2
Frequency (MHz) 4 4.193
4.2 System Clock
Generator
Table 4.2 Crystal
Oscillator Parameters
On-Chip Oscillator
Selection Method
(H8/38124 Group Only) 108 Note added
The on-chip oscillator is selected by setting the IRQAEC pin
input level during resets.
*
*
Other than watchdog timer or low-voltage detect circuit
reset.
4.4 Prescalers 111 Prescalers S (PPS)
Description amended
The output from prescaler S is shared by timer A, timer C, timer
F, timer G, SCI3, the A/D converter, the LCD controller,
watchdog timer, and the 10-bit PWM. The divider ratio can be
set separately for each on-chip peripheral function.
4.5.1 Definition of
Oscillation Stabilization
Wait Time 115 2. Wait time
Description amended, notes * 1, * 2 added
Oscillation stabilization wait time = oscillation stabilization time + wait time
= t
rc
+ (8 to 16,384 states)
* 1
................. (1)
(to 131,072 states)
* 2
Notes: 1. H8/38024 Group
2. H8/38124 Group
117 Table 5.1 amended
Operating Mode Description
5.1 Overview
Table 5.1 Operating
Modes
Watch mode The CPU halts. The time-base function of timer A, timer F,
timer G, AEC and LCD controller/driver are operable on the
subclock
5.5.2 Clearing
Subsleep Mode 132 • Clearing by interrupt
To synchronize is requested signal with the system clock, up to
2/
φ
SUB
(s) delay may occur after the interrupt request signal
occurrence, before the interrupt exception handling start.