Renesas H8/38024 Series, Hardware Manual

Page: 116 / 661

Rev. 6.00, 08/04, page 86 of 628
Bit 0—Asynchronous Event Counter Interrupt Request Flag (IRREC)
Bit 0
IRREC
Description
0 Clearing conditions: (initial value)
When IRREC = 1, it is cleared by writing 0
1 Setting conditions:
When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit
counter mode
Wakeup Interrupt Request Register (IWPR)
Bit
Initial value
Read/Write
7
IWPF7
0
R/(W)
*
6
IWPF6
0
R/(W)
*
5
IWPF5
0
R/(W)
*
4
IWPF4
0
R/(W)
*
3
IWPF3
0
R/(W)
*
0
IWPF0
0
R/(W)
*
2
IWPF2
0
R/(W)
*
1
IWPF1
0
R/(W)
*
Note:
*
Only a write of 0 for flag clearing is possible
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP
7
to
WKP
0
is designated for wakeup input and a rising or falling edge is input at that pin, the
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the
corresponding interrupt is accepted. Flags must be cleared by writing 0.
Bits 7 to 0—Wakeup Interrupt Request Flags (IWPF7 to IWPF0)
Bit n
IWPFn
Description
0 Clearing conditions: (initial value)
When IWPFn= 1, it is cleared by writing 0
1 Setting conditions:
When pin
WKP
n
is designated for wakeup input and a rising or falling edge is input at
that pin
(n = 7 to 0)