Renesas H8/38024 Series, Hardware Manual

Page: 326 / 661

Rev. 6.00, 08/04, page 296 of 628
Timer Counter W (TCW)
Bit
Initial value
Read/Write
7
TCW7
0
R/W
6
TCW6
0
R/W
5
TCW5
0
R/W
4
TCW4
0
R/W
3
TCW3
0
R/W
0
TCW0
0
R/W
2
TCW2
0
R/W
1
TCW1
0
R/W
For the H8/38024, H8/38024S, and H8/38024F-ZTAT groups, the clock source is
φ
/8,192 or
φ
w/32. For the H8/38124 group, the clock source is selected based on the timer mode register
(TMW) setting if WDCKS is 0 and is
φ
w/32 if WDCKS is 1.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.
Timer Mode Register (TMW)
Bit 7 6 5 4 3 2 1 0
— — — — CKS3 CKS2 CKS1 CKS0
Initial value 1 1 1 1 1 1 1 1
Read/Write — — — — R/W R/W R/W R/W
The TMW register is only implemented on the H8/38124. The input clock is selected using
combinations of CKS3 to CKS0.
Bits 7 to 4—Reserved
These bits are always read as 1.
Bits 3 to 0—Clock Select (CKS3 to CKS0)
These bits are used to select the clock input to TCW from among 10 internal options. Clock source
selection using this register is enabled when WDCKS in port mode register 2 (PMR2) is cleared to
0. If WDCKS is set to 1 the
φ
w/32 clock source is selected, regardless of the settings of the bits in
this register.