Renesas H8/38024 Series, Hardware Manual

Page: 352 / 661

Rev. 6.00, 08/04, page 322 of 628
10.1.3 Pin Configuration
Table 10.1 shows the SCI3 pin configuration.
Table 10.1 Pin Configuration
Name Abbr. I/O Function
SCI3 clock SCK
32
I/O SCI3 clock input/output
SCI3 receive data input RXD
32
Input SCI3 receive data input
SCI3 transmit data output TXD
32
Output SCI3 transmit data output
10.1.4 Register Configuration
Table 10.2 shows the SCI3 register configuration.
Table 10.2 Registers
Name Abbr. R/W Initial Value Address
Serial mode register SMR R/W H'00 H'FFA8
Bit rate register BRR R/W H'FF H'FFA9
Serial control register 3 SCR3 R/W H'00 H'FFAA
Transmit data register TDR R/W H'FF H'FFAB
Serial status register SSR R/W H'84 H'FFAC
Receive data register RDR R H'00 H'FFAD
Transmit shift register TSR Protected — —
Receive shift register RSR Protected — —
Bit rate counter BRC Protected — —
Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA
Serial port control register SPCR R/W — H'FF91