Olympus OEP-3, Service Manual

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4-6
OEP-3 V1 (UC)
4-1-3. Basic Operation Timing and CPU Block
The operation of the digital signal processing block on the VPR-63 board is controlled and managed
according to the command from the SY board by CPU.
CPU operates with the VD signal (SWD_VD) switched into EXT or INT as reference and performs each
setting and control for a DRAM control circuit (CXD911R).
The main functions of a CPU block for digital signal processing are as follows:
.
Reception and execution of command from SY board
.
VF judgment (synchronous management) of video input signal
.
Output of blanking signal
.
Control of DRAM control circuit
.
Write of color adjustment data
.
Write of caption data
.
Strobe-compatible
CPU memory map
The memory map of CPU is shown below.
00000
20000
C0000
C1000
C2000
C3000
FF710
FFF10
FFF1C
FFFFF
Program ROM
Color adjustment circuit (Monitor)
Color adjustment circuit (Print)
DRAM controller register
CPU internal SRAM
CPU internal register