Olympus OEP-3, Service Manual

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4-10
OEP-3 V1 (UC)
Write of color adjustment data
The data for a conversion table is written in CXD8869Q (color adjustment circuit) during V blanking.
Write of caption data
Caption data is set to a DRAM control circuit so as to output an access trigger (RATRG). The DRAM
control circuit expands the data on DRAM.
Strobe-compatible of IVP (e.g., certification photo)
A trigger signal for stroboscopic emission is output from a printer.
For the capture operation using an input signal from the REMOTE1 and 2 terminals and main unit’s key,
a trigger signal for stroboscopic emission is output from CPU during V period just before capture.
4-1-4. Memory (DRAM) Block
The memory block of a four-frame machine consists of 64M-bit SDRAM
x
1.
In the memory block of an eight-frame machine, one 64M-bit DRAM is added in addition to the
configuration of a four-frame machine.
64M-bit DRAM
x
2
The space in which two 64M-bit SDRAMs can be mounted is secured on the board. The number of
mounted SDRAMs varies depending on a four- or eight-frame machine.
CPU obtains the information on the number of mounted DRAMs by whether square-type chip conductors
(0
Z
resistors) R557 and R558 are mounted or not.
Model (Destination) 4F (R557) 8F (R558) Number of 64M-bit DRAMs
UP-50 (J/UC), 51MD (UC), 51MDP (CE) NM R558 2
UP-51MDU (UC) R557 NM 1
OPE-3 (J/UC) NM R558 2
The memory space is constituted by 600 (RAS) x 256 (CAS) x 32 bits for each color of one frame image
memory. However, the memory space is apparently considered as 600 (RAS)
x
1024 (CAS)
x
8 bits
during use by storing eight-bit image data proportionally to four-dot pixels (four-dot pixels in one
address) in the direction of depth. The conversion of eight bits to 32 bits and vice versa is performed
using a DRAM control circuit.
Model (Destination) DRAM reference
UP-50 (J/UC), 51MD (UC), 51MDP (CE) IC801,802
UP-51MDU (UC) IC801
OPE-3 (J/UC) IC801,802