Olympus OEP-3, Service Manual

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4-12
OEP-3 V1 (UC)
4-1-5. Memory Control Block
A four-dot pixel is stored in one address for high-speed processing using SDRAM of 32 bits in the
direction of depth so as to double the apparent SDRAM access speed. This processing is performed using
a standard cell circuit. The circuit is controlled by CPU.
Conversion of 8 bits to 32 bits and vice versa in case of input image data capture (FULL)
The eight-bit image data input to this circuit is stored in each line buffer in the order below.
The main operation and setting of a DRAM control circuit are as follows:
.
Various capture operations
FULL image
SPLIT 2 image
SPLIT 4 image
SPLIT 8 image (Decimated in the horizontal direction.)
SPLIT 16 image (Decimated in the horizontal direction.)
Capture shift size
Write DRAM address
By setting the items above, the DRAM control circuit automatically performs the capture operation in
synchronization with VD and HD signals.
.
Print data output operation
Number of output data items
Read DRAM address
The print data output operation is performed by setting the items above and by triggering from CPU.