4-15
OEP-3 V1 (UC)
4-1-7. Sampling Clock Generation Block
This block generates a sampling clock, locks the phase to the “high” level of external and internal sync
signals, and distributes the clock to the DRAM control circuit or color adjustment circuit.
The clock frequency is 17.897725 MHz for NTSC and 17.734475 MHz for PAL.
The operation timing is shown below.
Summary of Contents for OEP-3
Page 1: ...COLOR VIDEO PRINTER OEP 3 SERVICE MANUAL Volume 1 1st Edition...
Page 6: ......
Page 80: ......
Page 119: ...4 11 OEP 3 V1 UC Memory Configuration Eight Frame Memory Configuration Four Frame...
Page 154: ......
Page 165: ...5 11 OEP 3 V1 UC 5 5 Direct Chuck Mechanism...
Page 176: ...2000 9 22 OEP 3 UC E 9 955 247 11...