CHAPTER 16 I
2
C BUS
User’s Manual U16896EJ2V0UD
460
Figure 16-1. Block Diagram of I
2
C0
Internal bus
IIC status register 0 (IICS0)
IIC control register 0
(IICC0)
SO latch
IICE0
D Q
CL01,
CL00
TRC0
DFC0
DFC0
SDA0
SCL0
Output control
INTIIC0
IIC shift register 0
(IIC0)
IICC0.STT0, SPT0
IICS0.MSTS0, EXC0, COI0
IICS0.MSTS0,
EXC0, COI0
LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
Internal bus
CLD0 DAD0 SMC0 DFC0 CL01 CL00
CLX0
IIC clock select
register 0 (IICCL0)
STCF0 IICBSY0 STCEN0 IICRSV0
IIC flag register 0
(IICF0)
IIC function expansion
register 0 (IICX0)
f
XX
Clear
Slave address
register 0 (SVA0)
Match
signal
Set
Noise
eliminator
IIC shift
register 0 (IIC0)
Data
retention time
correction
circuit
N-ch open-drain
output
ACK detector
ACK
generator
Start condition
detector
Stop condition
detector
Serial clock counter
Serial clock
controller
Noise
eliminator
N-ch open-drain
output
Start
condition
generator
Stop
condition
generator
Wakeup controller
Interrupt request
signal generator
Serial clock
wait controller
Bus status
detector
Prescaler
<R>