CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U16896EJ2V0UD
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Figure 6-35. Basic Timing in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TP0CE bit
TIP0a pin input
TP0CCRa register
INTTP0CCa signal
INTTP0OV signal
TP0OVF bit
D
0
0000H
D
1
D
2
D
3
Cleared to 0 by
CLR instruction
Remark
a = 0, 1
When the TP0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIP0a pin is
later detected, the count value of the 16-bit counter is stored in the TP0CCRa register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTP0CCa) is generated.
The pulse width is calculated as follows.
Pulse width = Captured value
×
Count clock cycle
If the valid edge is not input to the TIP0a pin even when the 16-bit counter counted up to FFFFH, an overflow
interrupt request signal (INTTP0OV) is generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TP0OPT0.TP0OVF bit) is also set to 1. Clear the overflow flag to 0
by executing the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H
×
TP0OVF bit set (1) count + Captured value)
×
Count clock cycle
Remark
a = 0, 1
<R>
<R>
