CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART)
User’s Manual U16896EJ2V0UD
425
14.6.2 Serial clock generation
A serial clock can be generated according to the settings of the CKSRn and BRGCn registers.
The base clock to the 8-bit counter is selected by the CKSRn.TPSn3 to CKSRn.TPSn0 bits.
The 8-bit counter divisor value can be set by the BRGCn.MDLn7 to BRGCn.MDLn0 bits.
(1) Clock select register n (CKSRn)
The CKSRn register is an 8-bit register for selecting the base clock using the TPSn3 to TPSn0 bits. The
clock selected by the TPSn3 to TPSn0 bits becomes the base clock (f
UCLK
) of the transmission/reception
module.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution Clear the ASIMn.UARTEn bit to 0 before rewriting the TPSn3 to TPSn0 bits.
7
0
CKSRn
(n = 0, 1)
6
0
5
0
4
0
3
TPSn3
2
TPSn2
1
TPSn1
0
TPSn0
After reset: 00H R/W Address: CKSR0 FFFFFA06H, CKSR1 FFFFFA16H
TPSn3 TPSn2 TPSn1 TPSn0
Base
clock
(f
UCLK
)
Note 1
0 0 0 0
f
XX
0 0 0 1
f
XX
/2
0 0 1 0
f
XX
/4
0 0 1 1
f
XX
/8
0 1 0 0
f
XX
/16
0 1 0 1
f
XX
/32
0 1 1 0
f
XX
/64
0 1 1 1
f
XX
/128
1 0 0 0
f
XX
/256
1 0 0 1
f
XX
/512
1 0 1 0
f
XX
/1,024
1 0 1 1
External
clock
Note 2
(ASCK0 pin)
Other than above
Setting prohibited
Notes 1.
Set f
UCLK
so as to satisfy the following conditions.
•
V
DD
= 4.5 to 5.5 V: f
UCLK
≤
12 MHz
•
V
DD
= 2.7 to 4.5 V: f
UCLK
≤
6 MHz
2.
ASCK0 pin input clock can be used only by UART0.
Setting of UART1 is prohibited.
Remark
f
XX
: Main clock frequency
