CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U16896EJ2V0UD
154
(1) Interval timer mode operation flow
Figure 6-5. Software Processing Flow in Interval Timer Mode
FFFFH
16-bit counter
0000H
TP0CE bit
TP0CCR0 register
TOP00 pin output
INTTP0CC0 signal
D
0
D
0
D
0
D
0
<1>
<2>
TP0CE bit = 1
TP0CE bit = 0
Register initial setting
TP0CTL0 register
(TP0CKS0 to TP0CKS2 bits)
TP0CTL1 register,
TP0IOC0 register,
TP0CCR0 register
Initial setting of these registers is performed
before setting the TP0CE bit to 1.
The TP0CKS0 to TP0CKS2 bits can be
set at the same time when counting has
been started (TP0CE bit = 1).
The counter is initialized and counting is
stopped by clearing the TP0CE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow