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NEC V850ES/KE1+, User Manual


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APPENDIX  C   REGISTER  INDEX 

User’s Manual  U16896EJ2V0UD 

701

(2/6) 

Symbol Name 

Unit 

Page 

CSI0IC0 

Interrupt control register 

INTC 

548 

CSI0IC1 

Interrupt control register 

INTC 

548 

CSIC0 

Clocked serial interface clock selection register 0 

CSI0 

438 

CSIC1 

Clocked serial interface clock selection register 1 

CSI0 

438 

CSIM00 

Clocked serial interface mode register 00 

CSI0 

436 

CSIM01 

Clocked serial interface mode register 01 

CSI0 

436 

CTBP 

CALLT base pointer 

CPU 

48 

CTPC 

CALLT execution status saving register 

CPU 

47 

CTPSW 

CALLT execution status saving register 

CPU 

47 

DBPC 

Exception/debug trap status saving register 

CPU 

48 

DBPSW 

Exception/debug trap status saving register 

CPU 

48 

ECR 

Interrupt source register 

CPU 

45 

EIPC 

Interrupt status saving register 

CPU 

44 

EIPSW 

Interrupt status saving register 

CPU 

44 

FEPC 

NMI status saving register 

CPU 

45 

FEPSW 

NMI status saving register 

CPU 

45 

IIC0 

IIC shift register 0 

I

2

C 476 

IICC0 

IIC control register 0 

I

2

C 464 

IICCL0 

IIC clock selection register 0 

I

2

C 474 

IICF0 

IIC flag register 0 

I

2

C 472 

IICIC0 

Interrupt control register 

INTC 

548 

IICS0 

IIC status register 0 

I

2

C 469 

IICX0 

IIC function expansion register 0 

I

2

C 475 

IMR0 

Interrupt mask register 0 

INTC 

549 

IMR0H 

Interrupt mask register 0H 

INTC 

549 

IMR0L 

Interrupt mask register 0L 

INTC 

549 

IMR1 

Interrupt mask register 1 

INTC 

549 

IMR1H 

Interrupt mask register 1H 

INTC 

549 

IMR1L 

Interrupt mask register 1L 

INTC 

549 

IMR3 

Interrupt mask register 3 

INTC 

549 

IMR3L 

Interrupt mask register 3L 

INTC 

549 

INTF0 

External interrupt falling edge specification register 0 

INTC 

556 

INTF3 

External interrupt falling edge specification register 3 

INTC 

557 

INTF9H 

External interrupt falling edge specification register 9H 

INTC 

558 

INTR0 

External interrupt rising edge specification register 0 

INTC 

556 

INTR3 

External interrupt rising edge specification register 3 

INTC 

557 

INTR9H 

External interrupt rising edge specification register 9H 

INTC 

558 

ISPR 

In-service priority register 

INTC 

550 

KRIC 

Interrupt control register 

INTC 

548 

KRM 

Key return mode register 

KR 

571 

LVIIC 

Interrupt control register 

INTC 

548 

LVIM 

Low-voltage detection register 

LVI 

614 

LVIS 

Low-voltage detection level selection register 

LVI 

615 

NFC 

Digital noise elimination control register 

INTC 

554 

Summary of Contents for V850ES/KE1+

Page 1: ...0ES KE1 32 bit Single Chip Microcontrollers Hardware Printed in Japan User s Manual PD703302 PD703302Y PD70F3302 PD70F3302Y 2004 Document No U16896EJ2V0UD00 2nd edition Date Published August 2006 N CP...

Page 2: ...User s Manual U16896EJ2V0UD 2 MEMO...

Page 3: ...including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken...

Page 4: ...United States of America EEPROM is a trademark of NEC Electronics Corporation Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and or...

Page 5: ...fety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death...

Page 6: ...of electrical engineering logic circuits and microcontrollers To find the details of a register where the name is known Refer to APPENDIX C REGISTER INDEX To understand the details of an instruction...

Page 7: ...s However preliminary versions are not marked as such Documents related to V850ES KE1 Document Name Document No V850ES Architecture User s Manual U15943E V850ES KE1 Hardware User s Manual This manual...

Page 8: ...n of Unused Pins 36 2 3 Pin I O Circuits 38 CHAPTER 3 CPU FUNCTIONS 40 3 1 Features 40 3 2 CPU Register Set 41 3 2 1 Program register set 42 3 2 2 System register set 43 3 3 Operating Modes 49 3 4 Add...

Page 9: ...6 5 1 Interval timer mode TP0MD2 to TP0MD0 bits 000 151 6 5 2 External event count mode TP0MD2 to TP0MD0 bits 001 161 6 5 3 External trigger pulse output mode TP0MD2 to TP0MD0 bits 010 169 6 5 4 One...

Page 10: ...8 4 5 Operation as interval timer 16 bits 308 8 4 6 Operation as external event counter 16 bits 310 8 4 7 Square wave output operation 16 bit resolution 311 8 4 8 Cautions 312 CHAPTER 9 8 BIT TIMER H...

Page 11: ...Registers 368 13 5 Operation 377 13 5 1 Basic operation 377 13 5 2 Trigger modes 378 13 5 3 Operation modes 379 13 5 4 Power fail detection function 382 13 5 5 Setting method 383 13 6 Cautions 385 13...

Page 12: ...ol Methods 478 16 5 1 Start condition 478 16 5 2 Addresses 479 16 5 3 Transfer direction specification 479 16 5 4 ACK 480 16 5 5 Stop condition 481 16 5 6 Wait state 482 16 5 7 Wait state cancellation...

Page 13: ...rupts 543 17 3 4 Interrupt control register xxlCn 547 17 3 5 Interrupt mask registers 0 1 3 IMR0 IMR1 IMR3 549 17 3 6 In service priority register ISPR 550 17 3 7 ID flag 551 17 3 8 Watchdog timer mod...

Page 14: ...eck Reset Source 590 20 4 Reset Sources 591 20 4 1 Reset operation via RESET pin 591 20 4 2 Reset operation by WDTRES1 signal 595 20 4 3 Reset operation by WDTRES2 signal 596 20 4 4 Power on clear res...

Page 15: ...Functional Outline 628 26 4 Rewriting by Dedicated Flash Programmer 632 26 4 1 Programming environment 632 26 4 2 Communication mode 633 26 4 3 Flash memory control 638 26 4 4 Selection of communicat...

Page 16: ...4 1 When using IECUBE QB V850ESKX1H 684 A 4 2 When using MINICUBE QB V850MINI 686 A 5 Debugging Tools Software 688 A 6 Embedded Software 689 A 7 Flash Memory Writing Tools 689 APPENDIX B INSTRUCTION...

Page 17: ...ower flash 256 KB RAM 12 KB PD703211Y PD703211 Mask ROM 256 KB RAM 12 KB V850ES KF1 PD70F3308Y PD70F3308 Single power flash 256 KB RAM 12 KB PD703308Y PD703308 Mask ROM 256 KB RAM 12 KB PD703214Y PD70...

Page 18: ...h Automatic transmit receive 3 wire CSI 1 ch 2 ch 2 ch UART 1 ch 1 ch 2 ch 2 ch UART supporting LIN bus 1 ch 1 ch 1 ch 1 ch Serial interface I2 CNote 2 1 ch 1 ch 1 ch 2 ch Address space 128 KB 3 MB 15...

Page 19: ...O 6 bits 1 ch 6 bits 1 ch 6 bits 1 ch 6 bits 2 ch CSI 2 ch 2 ch 2 ch 3 ch Automatic transmit receive 3 wire CSI 1 ch 2 ch 2 ch UART 2 ch 2 ch 2 ch 3 ch UART supporting LIN bus Serial interface I2 CNot...

Page 20: ...65 mm pitch Single power flash 32 KB RAM 1 KB Single power flash 24 KB RAM 1 KB Single power flash 16 KB RAM 512 B 78K0 KD1 PD78F0123H PD78F0124H HDNote PD78F0122H 78K0 KD1 Two power flash 32 KB RAM...

Page 21: ...watch 1 ch Timer WDT 1 ch 3 wire CSI Note 3 1 ch 2 ch 1 ch 2 ch Automatic transmit receive 3 wire CSI 1 ch UART Note 3 1 ch Serial interface UART supporting LIN bus 1 ch 10 bit A D converter 4 ch 8 c...

Page 22: ...h 8 bits TMH 2 ch For watch 1 ch Timer WDT 1 ch 3 wire CSI Note 2 1 ch 2 ch Automatic transmit receive 3 wire CSI 1 ch UART Note 2 1 ch Serial interface UART supporting LIN bus 1 ch 10 bit A D convert...

Page 23: ...ap 1 source I O lines Total 51 Key interrupt function Timer function 16 bit timer event counter P 1 channel 16 bit timer event counter 0 1 channel 8 bit timer event counter 5 2 channels 8 bit timer H...

Page 24: ...try reception etc Submicrocontroller of control system Home audio car audio AV equipment PC peripheral devices keyboards etc Household appliances Outdoor units of air conditioners Microwave ovens rice...

Page 25: ...01 P33 TIP00 TOP00 P34 TIP01 TOP01 P35 TI010 TO01 P50 KR0 TI011 RTP00 P51 KR1 TI50 RTP01 P52 KR2 TO50 RTP02 P53 KR3 RTP03 EV SS PDL1 PDL0 PCM1 CLKOUT PCM0 P915 INTP6 P914 INTP5 P913 INTP4 P99 SCK01 P9...

Page 26: ...connection NMI Non maskable interrupt request P00 to P06 Port 0 P30 to P35 P38 P39 Port 3 P40 to P42 Port 4 P50 to P55 Port 5 P70 to P77 Port 7 P90 P91 P96 to P99 P913 to P915 Port 9 PCM0 PCM1 Port CM...

Page 27: ...to P06 AV REF0 AV SS ANI0 to ANI7 ADTRG ICNote 3 EVDD EVSS FLMD0 FLMD1Note 4 VSS BCU POC LVI CG CLKOUT X1 X2 XT1 XT2 RESET VDD 16 bit timer event counter 0 1 ch 16 bit timer event counter P 1 ch 8 bi...

Page 28: ...nterrupt priorities can be specified for these interrupt requests and multiplexed servicing control can be performed f Clock generator CG A main clock oscillator and subclock oscillator are provided a...

Page 29: ...I0n and SCK0n pins For I2 C0 data is transferred via the SDA0 and SCL0 pins I 2 C0 is provided only in the PD703302Y and 70F3302Y Remark n 0 1 k A D converter This high speed high resolution 10 bit A...

Page 30: ...below the following ports have general purpose port functions and control pin functions Port I O Alternate Function P0 7 bit I O NMI external interrupt timer output P3 8 bit I O Serial interface timer...

Page 31: ...ain output selectable 4 fixed to N ch open drain output 2 Timer 16 bit timer event counter P 1 channel 16 bit timer event counter 0 1 channel 8 bit timer event counter 5 2 channels 16 bit timer event...

Page 32: ...ction P00 12 TOH0 P01 13 TOH1 P02 14 NMI P03 15 INTP0 P04 16 INTP1 P05 17 INTP2 P06 18 I O Yes Port 0 I O port Input output can be specified in 1 bit units INTP3 P30 22 TXD0 P31 23 RXD0 INTP7 P32 24 A...

Page 33: ...58 ANI6 P77 57 Input No Port 7 Input port ANI7 P90 36 TXD1 KR6 P91 37 RXD1 KR7 P96 38 TI51 TO51 P97 39 SI01 P98 40 SO01 P99 41 SCK01 P913 42 INTP4 P914 43 INTP5 P915 44 I O Yes Port 9 I O port Input o...

Page 34: ...32 Ground potential for external FLMD0 Note 1 3 No FLMD1 Note 1 52 Input Yes Flash programming mode setting pin PDL5 IC Note 2 3 Internally connected INTP0 15 P03 INTP1 16 P04 INTP2 17 External inter...

Page 35: ...n output can be specified in 1 bit units P98 TI010 27 Capture trigger input external event input for TM01 P35 TO01 TI011 28 Capture trigger input for TM01 P50 RTP00 KR0 TI50 29 External event input fo...

Page 36: ...E P42 SCK00 21 10 F P50 TI011 RTP00 KR0 28 P51 TI50 RTP01 KR1 29 P52 TO50 RTP02 KR2 30 P53 RTP03 KR3 31 8 A P54 RTP04 KR4 34 P55 RTP05 KR5 35 10 A Input Independently connect to EVDD or EVSS via a re...

Page 37: ...t to EVSS or VSS or pull down with a 10 k resistor NC 5 Leave open RESET 9 2 Connect to EVDD via a resistor FLMD0 Note 2 3 Directly connect to EVSS or VSS or pull down with a 10 k resistor VDD 4 VSS 6...

Page 38: ...ator AVREF0 threshold voltage P ch N ch Input enable Pull up enable Data Output disable VDD P ch VDD P ch IN OUT N ch Pull up enable Data Output disable Input enable VDD P ch VDD P ch IN OUT N ch Data...

Page 39: ...6896EJ2V0UD 39 2 2 Type 16 P ch Feedback cut off XT1 XT2 Type 13 AE Data Output disable Input enable IN OUT N ch VSS Mask option VDD Type 13 AD Data Output disable Input enable IN OUT N ch VSS Remark...

Page 40: ...e 50 0 ns 20 MHz operation 4 5 to 5 5 V 100 ns 10 MHz operation 2 7 to 5 5 V Memory space Program physical address space 64 MB linear Data logical address space 4 GB linear General purpose registers 3...

Page 41: ...r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 Zero register Assembler reserved register Stack pointer SP Global pointer GP Text pointer TP Element pointer EP Link pointer LP PC Program coun...

Page 42: ...sed by the real time OS r2 can be used as a variable register Table 3 1 Program Registers Name Usage Operation r0 Zero register Always holds 0 r1 Assembler reserved register Working register for gener...

Page 43: ...on is not guaranteed if accessed No No 16 CALLT execution status saving register CTPC Yes Yes 17 CALLT execution status saving register CTPSW Yes Yes 18 Exception debug trap status saving register DBP...

Page 44: ...or maskable interrupt occurs is saved to EIPC except for some instructions refer to 17 9 Periods in Which Interrupts Are Not Acknowledged by CPU The current PSW contents are saved to EIPSW Since there...

Page 45: ...rrupt servicing is performed Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved fixed to 0 for future function expansion 31 0 FEPC PC contents saved 0 0 After reset 0xxxxxxxH x Undefined 262...

Page 46: ...upt requests can be acknowledged even when this bit is set 0 Exception processing not in progress 1 Exception processing in progress 5 ID Indicates whether maskable interrupt request acknowledgment is...

Page 47: ...tual operation result 5 CALLT execution status saving registers CTPC CTPSW There are two CALLT execution status saving registers CTPC and CTPSW When the CALLT instruction is executed the contents of t...

Page 48: ...an exception trap or debug trap occurs The current PSW contents are saved to DBPSW Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved fixed to 0 for future function expansion 31 0 DBPC PC c...

Page 49: ...rammed by using a flash programmer a Specifying operating mode The operating mode is specified according to the status input level of the FLMD0 and FLMD1 pins In the normal operating mode input a low...

Page 50: ...data space is supported The 4 GB address space however is viewed as 64 images of a 64 MB physical address space This means that the same 64 MB physical address space is accessed regardless of the val...

Page 51: ...these addresses Caution No instructions can be fetched from the 4 KB area of 03FFF000H to 03FFFFFFH because this area is an on chip peripheral I O area Therefore do not execute any branch operation i...

Page 52: ...areas as shown below Figure 3 2 Data Memory Map Physical Addresses 3FFFFFFH 3FEC000H 3FEBFFFH 0100000H 00FFFFFH 0000000H 3FFF000H 3FFEFFFH 3FFF000H 3FFEFFFH 3FFFFFFH 3FEC000H 80 KB Use prohibited area...

Page 53: ...Figure 3 3 Program Memory Map 03FF0000H 03FEFFFFH 03FFF000H 03FFEFFFH 03FFFFFFH 00100000H 000FFFFFH 00000000H Internal RAM area 60 KB Use prohibited area Program fetch disabled area Use prohibited ar...

Page 54: ...FFFH 0020000H 001FFFFH 0000000H Access prohibited area Internal ROM area 128 KB 2 Internal RAM area An area of 60 KB maximum from 3FF0000H to 3FFEFFFH is reserved for the internal RAM area a Internal...

Page 55: ...ss bits 2 If a register that can be accessed in byte units is accessed in halfword units the higher 8 bits become undefined if the access is a read operation If a write access is performed only the da...

Page 56: ...ting from 00000000H unconditionally corresponds to the memory map To use the internal RAM area as the program space access the addresses 3FFE000H to 3FFEFFFH 4 KB 2 Data space With the V850ES KE1 it s...

Page 57: ...F F F F H 0 3 F F F 0 0 0 H 0 3 F F E F F F H 0 3 F F E 0 0 0 H 0 3 F F D F F F H 0 3 F F 0 0 0 0 H 0 3 F E F F F F H 0 0 0 2 0 0 0 0 H 0 0 0 1 F F F F H 0 0 1 0 0 0 0 0 H 0 0 0 F F F F F H 0 0 0 0 0...

Page 58: ...Interrupt control register PIC2 R W 47H FFFFF118H Interrupt control register PIC3 R W 47H FFFFF11AH Interrupt control register PIC4 R W 47H FFFFF11CH Interrupt control register PIC5 R W 47H FFFFF11EH...

Page 59: ...ister H ADCRH R Undefined FFFFF300H Key return mode register KRM R W 00H FFFFF308H Selector operation control register 0 SELCNT0 R W 00H FFFFF30AH Selector operation control register 1 SELCNT1 R W 00H...

Page 60: ...8 bit timer H compare register 01 CMP01 R W 00H FFFFF590H 8 bit timer H mode register 1 TMHMD1 R W 00H FFFFF591H 8 bit timer H carrier control register 1 TMCYC1 R W 00H FFFFF592H 8 bit timer H compare...

Page 61: ...Watch timer operation mode register WTM R W 00H FFFFF6C0H Oscillation stabilization time selection register OSTS R W Note FFFFF6C1H Watchdog timer clock selection register WDCS R W 00H FFFFF6C2H Watc...

Page 62: ...rrection control register CORCN R W 00H FFFFF888H Reset source flag register RESF R W Note FFFFF890H Low voltage detection register LVIM R W 00H FFFFF891H Low voltage detection level selection registe...

Page 63: ...erface clock selection register 0 CSIC0 R W 00H FFFFFD02H Clocked serial interface receive buffer register 0 SIRB0 R 0000H FFFFFD02H Clocked serial interface receive buffer register 0L SIRB0L R 00H FF...

Page 64: ...W 00H FFFFFD82H IIC control register 0 IICC0 Note R W 00H FFFFFD83H Slave address register 0 SVA0 Note R W 00H FFFFFD84H IIC clock selection register 0 IICCL0 Note R W 00H FFFFFD85H IIC function expa...

Page 65: ...from unexpectedly stopping due to an inadvertent program loop Write access to the special registers is performed with a special sequence and illegal store operations are notified to the SYS register 1...

Page 66: ...may not be realized when an interrupt is acknowledged for that instruction which may cause malfunction 2 The data written to the PRCMD register is dummy data but use the same register as the general...

Page 67: ...to an on chip peripheral I O register other than a special register is performed following write to the PRCMD register when 3 in 3 4 7 1 Setting data to special registers is not a special register Re...

Page 68: ...s 32 kHz fCLK 8 3 MHz 00H 0 no waits 2 7 V VDD 4 0 V 8 3 MHz fCLK 10 MHz 01H 1 b Access to special on chip peripheral I O register This product has two types of internal system buses One type is for t...

Page 69: ...the calculation of number of waits the fractional part of its result must be multiplied by 1 fCPU and rounded down if 1 fCPU 2 m or lower and rounded up if 1 fCPU 2 m is exceeded 2 I2 C0 is available...

Page 70: ...subr reg1 reg2 cmp reg1 reg2 sar imm5 reg2 satsub reg1 reg2 xor reg1 reg2 sub reg1 reg2 cmp imm5 reg2 shl imm5 reg2 Example i ld w r11 r10 If the decode operation of the mov instruction ii immediately...

Page 71: ...The V850ES KE1 incorporates a total of 51 I O port pins consisting of ports 0 3 to 5 7 9 CM and DL including 8 input only port pins The port configuration is shown below P00 P06 Port 0 P90 P91 P96 P9...

Page 72: ...0 3 to 5 7 9 CM DL Port n mode register PMn n 0 3 to 5 9 CM DL Port n mode control register PMCn n 0 3 to 5 9 CM Port n function control register PFCn n 3 5 9 Port n function register PFn n 3 4 9 Por...

Page 73: ...Register Setting of PMn Register Writing to Pn Register Reading from Pn Register Output mode PMnm bit 0 Write to the output latch Note The contents of the output latch are output from the pin The valu...

Page 74: ...tput mode Input mode PMnm 0 1 Control of I O mode PMn6 PMn5 PMn4 PMn3 PMn2 PMn1 PMn0 PMn After reset FFH R W 3 Port n mode control register PMCn PMCn specifies the port mode alternate function Each bi...

Page 75: ...e function 2 PFCnm 0 1 Specification of alternate function 5 Port n function control expansion register PFCEn PFCEn is a register that specifies the alternate function to be used when one pin has thre...

Page 76: ...ter When the PMnm bit is 1 input mode the set value in the PFn register is invalid Example 1 When the value of the PFn register is valid PFnm bit 1 N ch open drain output is specified PMnm bit 0 Outpu...

Page 77: ...r Alternate function when three or more alternate functions are available Alternate function 1 Alternate function 2 Alternate function 3 Alternate function 4 PFCn register PFCEn register PFCEnm 0 1 0...

Page 78: ...og digital noise elimination D1 SUIL Notes 1 Software pull up function 2 Only the P00 pin outputs a low level after reset other port pins are in input mode Therefore the low level output from the P00...

Page 79: ...eration mode I O port INTP0 input PMC03 0 1 Specification of P03 pin operation mode I O port NMI input PMC02 0 1 Specification of P02 pin operation mode I O port TOH1 output PMC01 0 1 Specification of...

Page 80: ...RXD0 INTP7 Input D1 SUIHL 24 P32 ASCK0 ADTRG TO01 I O E10 SUL 25 P33 TIP00 TOP00 I O Gxx10 SUL 26 P34 TIP01 TOP01 I O Gxx10 SUL 27 P35 TI010 TO01 I O Yes E10 SUL 55 P38 SDA0 Note 2 I O D2 SNMUFH 56 P...

Page 81: ...gister are used as the P3H register and as the P3L register respectively this register can be read or written in 8 bit or 1 bit units 2 Port 3 mode register PM3 1 Output mode Input mode PM3n 0 1 Contr...

Page 82: ...0000H R W Address PMC3 FFFFF446H PMC3L FFFFF446H PMC3H FFFFF447H 0 0 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 0 0 0 0 0 0 PMC39Note 2 PMC38Note 2 8 9 10 11 12 13 14 15 PMC3L Notes 1 When reading from or wr...

Page 83: ...owing sequence Be sure to set the port latch to 1 before setting the pin to N ch open drain output P3n bit 1 PF3n bit 1 PMC3n bit 1 5 Port 3 function control register PFC3 PFC3 After reset 00H R W Add...

Page 84: ...er input of the alternate function ADTRG pin clear the ADS TRG bit to 0 or set the ADS ADTMD bit to 1 When using the pin as the ADTRG pin do not set the UART0 operation clock to external input set the...

Page 85: ...put D0 UF 21 P42 SCK00 I O Yes N ch open drain output can be selected D2 SUFL Note Software pull up function Caution P40 and P42 have hysteresis characteristics when the alternate function is input bu...

Page 86: ...gister PF4 0 Normal output N ch open drain output PF4n 0 1 Control of normal output N ch open drain output n 1 2 PF4 0 0 0 0 PF42 PF41 0 After reset 00H R W Address FFFFFC68H Caution When using P41 an...

Page 87: ...SULT 29 P51 TI50 RTP01 KR1 I O E10 SULT 30 P52 TO50 RTP02 KR2 I O E00 SUT 31 P53 RTP03 KR3 I O Ex0 SUT 34 P54 RTP04 KR4 I O Ex0 SUT 35 P55 RTP05 KR5 I O Yes Ex0 SUT Note Software pull up function 1 P...

Page 88: ...mode 0 0 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 After reset 00H R W Address FFFFF44AH PMC5 I O port KR3 input RTP03 output PMC53 0 1 Specification of P53 pin operation mode I O port KR2 input TO50 output...

Page 89: ...PFC53 1 Specification of alternate function pin of P53 pin RTP04 output PFC54 1 Specification of alternate function pin of P54 pin After reset 00H R W Address FFFFF46AH 0 0 PFC55 PFC54 PFC53 PFC52 PF...

Page 90: ...Pin No Pin Name Alternate Function I O PULL Note Remark Block Type 64 P70 ANI0 Input A A 63 P71 ANI1 Input A A 62 P72 ANI2 Input A A 61 P73 ANI3 Input A A 60 P74 ANI4 Input A A 59 P75 ANI5 Input A A 5...

Page 91: ...emark Block Type 36 P90 TXD1 KR6 I O Ex0 SUT 37 P91 RXD1 KR7 Input Ex1 SUHT 38 P96 TI51 TO51 I O Ex0 SUT 39 P97 SI01 Input Ex1 SUL 40 P98 SO01 Output Ex0 UF 41 P99 SCK01 I O N ch open drain output can...

Page 92: ...are used as the P9H register and as the P9L register respectively these registers can be read or written in 8 bit or 1 bit units 2 Port 9 mode register PM9 PM97 Output mode Input mode PM9n 0 1 Contro...

Page 93: ...C98 0 1 Specification of P98 pin operation mode PMC9L I O port SI01 input PMC97 0 1 Specification of P97 pin operation mode I O port TI51 input TO51 output PMC96 0 1 Specification of P96 pin operation...

Page 94: ...normal output N ch open drain output n 8 9 PF9H 0 0 0 0 0 PF99 PF98 After reset 00H R W Address FFFFFC73H Caution When using P98 and P99 as N ch open drain output alternate function pins set in the f...

Page 95: ...C91 PFC90 PFC915 PFC914 PFC913 0 0 0 PFC99 PFC98 8 9 10 11 12 13 14 15 SCK01 I O PFC99 1 Specification of alternate function pin of P99 pin SO01 output PFC98 1 Specification of alternate function pin...

Page 96: ...0 0 0 0 PU91 PU90 PU915 PU914 PU913 0 0 0 PU99 PU98 8 9 10 11 12 13 14 15 PU9L Note When reading from or writing to bits 8 to 15 of the PU9 register in 8 bit or 1 bit units specify these bits as bits...

Page 97: ...Yes D0 U Note Software pull up function 1 Port CM register PCM 0 is output 1 is output PCMn 0 1 Control of output data in output mode n 0 1 After reset 00H output latch R W Address FFFFF00CH 0 PCM 0...

Page 98: ...ser s Manual U16896EJ2V0UD 98 4 Pull up resistor option register CM PUCM Not connected Connected PUCMn 0 1 Control of on chip pull up resistor connection n 0 1 After reset 00H R W Address FFFFFF4CH 0...

Page 99: ...be controlled in 1 bit units Port DL includes the following alternate functions Table 4 11 Alternate Function Pins of Port DL Pin No Pin Name Alternate Function I O PULL Note Remark Block Type 47 PDL...

Page 100: ...PDL3 PDL2 PDL1 PDL0 PDL 2 Port DL mode register PMDL PMDL7 Output mode Input mode PMDLn 0 1 Control of I O mode n 0 to 7 PMDL6 PMDL5 PMDL4 PMDL3 PMDL2 PMDL1 PMDL0 After reset FFH R W Address FFFFF024...

Page 101: ...V0UD 101 4 4 Block Diagrams Figure 4 2 Block Diagram of Type A A Internal bus RD A D input signal Pmn P ch N ch Figure 4 3 Block Diagram of Type C U WRPM RD WRPORT Pmn PMmn WRPU EVDD PUmn P ch Address...

Page 102: ...er s Manual U16896EJ2V0UD 102 Figure 4 4 Block Diagram of Type D0 U WRPMC RD Address Output signal of alternate function 1 WRPORT Pmn PMCmn WRPU PUmn WRPM PMmn EVDD P ch Output latch Pmn Internal bus...

Page 103: ...896EJ2V0UD 103 Figure 4 5 Block Diagram of Type D0 UF WRPMC RD WRPORT Pmn PMCmn WRPU PUmn WRPM PMmn WRPF PFmn EVDD P ch EVDD EVSS P ch N ch Address Output latch Pmn Internal bus Selector Selector Sele...

Page 104: ...lternate function 1 WRPORT Pmn Note 2 PMCmn WRINTF INTFmnNote 1 WRPU PUmn WRPM PMmn Noise elimination Edge detection WRINTR INTRmnNote 1 EVDD P ch Output latch Pmn Internal bus Selector Selector Notes...

Page 105: ...WRINTF INTFmnNote 1 WRINTR INTRmnNote 1 EVDD P ch Input signal of alternate function 1 2 Input signal of alternate function 1 1 Noise elimination Edge detection Output latch Pmn Note 2 Internal bus Se...

Page 106: ...Figure 4 8 Block Diagram of Type D1 SUL WRPMC RD WRPORT Address Pmn PMCmn WRPU PUmn WRPM PMmn EVDD P ch Note Output latch Pmn Internal bus Selector Selector Input signal of alternate function 1 Note...

Page 107: ...D2 SNMUFH WRPMC RD Address Output signal of alternate function 1 Input signal of alternate function 1 WRPORT PMCmn WRPF PFmn WRPM PMmn Pmn EVDD EVSS Note Mask option N ch Output latch Pmn Internal bus...

Page 108: ...T Pmn PMCmn WRPU PUmn WRPM PMmn WRPF PFmn EVDD P ch EVDD EVSS P ch N ch Address Output latch Pmn Internal bus Selector Selector Selector Input signal of alternate function 1 Output signal of alternate...

Page 109: ...m of Type E00 SUT WRPMC RD Address Alternate function input signal in port mode Output signal of alternate function 2 Output signal of alternate function 1 WRPORT Pmn PMCmn WRPU PUmn WRPM PMmn WRPFC P...

Page 110: ...ype E10 SUL WRPMC RD Address Input signal of alternate function 1 Output signal of alternate function 2 WRPORT Pmn PMCmn WRPU PUmn WRPM PMmn WRPFC PFCmn EVDD P ch Output latch Pmn Internal bus Selecto...

Page 111: ...iagram of Type E10 SULT WRPMC RD Address Alternate function input signal in port mode Input signal of alternate function 1 Output signal of alternate function 2 WRPORT Pmn PMCmn WRPU PUmn WRPM PMmn WR...

Page 112: ...Figure 4 14 Block Diagram of Type Ex0 SUT WRPMC RD Address Alternate function input signal in port mode Output signal of alternate function 2 WRPORT Pmn PMCmn WRPU PUmn WRPM PMmn WRPFC PFCmn EVDD P ch...

Page 113: ...0UD 113 Figure 4 15 Block Diagram of Type Ex0 UF WRPMC RD Address Output signal of alternate function 2 WRPORT Pmn PMCmn WRPFC PFCmn WRPU PUmn WRPM PMmn WRPF PFmn EVDD P ch EVDD EVSS P ch N ch Output...

Page 114: ...114 Figure 4 16 Block Diagram of Type Ex1 SUHT WRPMC RD WRPORT Pmn PMCmn WRPU PUmn WRPM PMmn WRPFC PFCmn EVDD P ch Output latch Pmn Address Input signal of alternate function 2 Alternate function inpu...

Page 115: ...RPU PUmn WRPM PMmn WRINTF INTFmnNote 1 WRINTR INTRmnNote 1 EVDD P ch Output latch Pmn Note 2 Address Input signal of alternate function 2 Noise elimination Edge detection Internal bus Selector Selecto...

Page 116: ...s Manual U16896EJ2V0UD 116 Figure 4 18 Block Diagram of Type Ex1 SUL WRPMC RD WRPORT Pmn PMCmn WRPU PUmn WRPM PMmn WRPFC PFCmn EVDD P ch Output latch Pmn Address Input signal of alternate function 2 I...

Page 117: ...gnal of alternate function 2 Output signal of alternate function 2 WRPORT Pmn Note PMCmn WRPFC PFCmn WRPU PUmn WRPM PMmn WRPF PFmn EVDD P ch EVDD EVSS P ch N ch Output latch Pmn Output enable signal o...

Page 118: ...0 SUL P ch WRPMC RD WRPORT Pmn Note PMCmn WRPFCE PFCEmn WRPM PMmn WRPFC PFCmn WRPU PUmn EVDD Address Input signal of alternate function 3 Output signal of alternate function 4 Output latch Pmn Interna...

Page 119: ...J2V0UD 119 4 5 Port Register Setting When Alternate Function Is Used Table 4 12 shows the port register settings when each port is used for an alternate function When using a port pin as an alternate...

Page 120: ...tting not required P30 Setting not required P31 Setting not required P31 Setting not required P32 Setting not required P32 Setting not required P32 Setting not required P33 Setting not required P33 Se...

Page 121: ...ed PM54 1 PM55 Setting not required PM55 1 Pnx Bit of Pn Register P50 Setting not required P50 Setting not required P50 Setting not required P51 Setting not required P51 Setting not required P51 Setti...

Page 122: ...ed P96 Setting not required P96 Setting not required P97 Setting not required P98 Setting not required P99 Setting not required I O Output Input Input Input Input Output Input Output I O Alternate Fun...

Page 123: ...tion is executed in the following order in the V850ES KE1 1 The Pn register is read in 8 bit units 2 The targeted one bit is manipulated 3 The Pn register is written in 8 bit units In step 1 the value...

Page 124: ...PORT FUNCTIONS User s Manual U16896EJ2V0UD 124 4 6 2 Hysteresis characteristics In port mode the following ports do not have hysteresis characteristics P02 to P06 P31 to P35 P38 P39 P40 P42 P97 P99 P9...

Page 125: ...V Subclock oscillator fXT 32 768 kHz Internal oscillator fR 120 to 480 kHz 240 kHz TYP Multiplication 4 function by PLL Phase Locked Loop Clock through mode PLL mode selectable Usable voltage VDD 2 7...

Page 126: ...Watchdog timer 1 clock Watchdog timer 2 clock fR 2048 TMH1 clock Internal system clock fXX to fXX 1024 fXW Selector Selector Selector Selector CK2 to CK0 bits IDLE mode IDLE mode IDLE control IDLE con...

Page 127: ...UART0 UART1 I2 C0 and ADC 5 Prescaler 2 This circuit divides the main clock fXX The clock generated by prescaler 2 fXX to fXX 32 is supplied to the selector that generates the CPU clock fCPU and inte...

Page 128: ...ation stopped MCK 0 1 Control of main clock oscillator Used Not used MFRC 0 1 Use of main clock on chip feedback resistor After reset 03H R W Address FFFFF828H Main clock operation Subclock operation...

Page 129: ...KOUT is being output 2 Use a bit manipulation instruction to manipulate the CK3 bit When using an 8 bit manipulation instruction do not change the set values of the CK2 to CK0 bits 3 When the CPU oper...

Page 130: ...s 1 When stopping the main clock stop the PLL 2 If the following conditions are not satisfied change the CK2 to CK0 bits so that the conditions are satisfied then change to the subclock operation mode...

Page 131: ...s started Max 1 fXT 1 subclock frequency Therefore insert one NOP instruction immediately after setting the CK3 bit to 0 or read the CLS bit to check if main clock operation has started Description ex...

Page 132: ...by software is selected by the mask option Flash memory version PD70F3302 70F3302Y Valid when the RSTP bit is cleared to 0 by the option byte setting 0 RCM 0 0 0 0 0 0 RSTOP After reset 00H R W Addre...

Page 133: ...function is used to output the internal system clock fCLK from the CLKOUT pin The internal system clock fCLK is selected by using the PCC CK3 to PCC CK0 bits The CLKOUT pin functions alternately as th...

Page 134: ...to 10 MHz 5 5 2 Register 1 PLL control register PLLCTL The PLLCTL register is an 8 bit register that controls the security function of PLL and RTO This register can be read or written in 8 bit or 1 bi...

Page 135: ...mode first enable PLL operation PLLON bit 1 and then select the PLL mode SELPLL bit 1 To enable the PLL operation first set the PLLON bit to 1 wait for 200 s and then set the SELPLL bit to 1 To stop...

Page 136: ...tion 8 ways Capture trigger input pins 2 External event count input pins 1 External trigger input pins 1 Timer counters 1 Capture compare registers 2 Capture compare match interrupt request signals 2...

Page 137: ...ontrol registers 0 1 TP0CTL0 TP0CTL1 TMP0 I O control registers 0 to 2 TP0IOC0 to TP0IOC2 TMP0 option register 0 TP0OPT0 Note The TIP00 pin functions alternately as a capture trigger input signal exte...

Page 138: ...mpare register that compares the count value of the 16 bit counter When the TP0CCR1 register is used as a compare register the value written to the TP0CCR1 register is transferred to the CCR1 buffer r...

Page 139: ...operation enabled TMP0 operation started TP0CE 0 1 TMP0 operation control TP0CTL0 0 0 0 0 TP0CKS2 TP0CKS1 TP0CKS0 6 5 4 3 2 1 After reset 00H R W Address FFFFF5A0H 7 0 fXX fXX 2 fXX 4 fXX 8 fXX 16 fXX...

Page 140: ...with the internal count clock or the valid edge of the external event count input 7 0 Interval timer mode External event count mode External trigger pulse output mode One shot pulse output mode PWM ou...

Page 141: ...starts output at high level TOP00 pin starts output at low level TP0OE0 0 1 TOP00 pin output setting Timer output disabled When TP0OL0 bit 0 Low level is output from the TOP00 pin When TP0OL0 bit 1 H...

Page 142: ...dge Detection of both edges TP0IOC1 0 0 0 TP0IS3 TP0IS2 TP0IS1 TP0IS0 6 5 4 3 2 1 After reset 00H R W Address FFFFF5A3H TP0IS1 0 0 1 1 TP0IS0 0 1 0 1 Capture trigger input signal TIP00 pin valid edge...

Page 143: ...et 00H R W Address FFFFF5A4H TP0ETS1 0 0 1 1 TP0ETS0 0 1 0 1 External trigger input signal TIP00 pin valid edge setting No edge detection external trigger invalid Detection of rising edge Detection of...

Page 144: ...overflow detection flag The TP0OVF bit is set when the 16 bit counter count value overflows from FFFFH to 0000H in the free running timer mode or the pulse width measurement mode An interrupt request...

Page 145: ...e used only as a capture register In any other mode this register can be used only as a compare register The TP0CCR0 register can be read or written during operation This register can be read or writt...

Page 146: ...e of the 16 bit counter is stored in the TP0CCR0 register if the valid edge of the capture trigger input pin TIP00 pin is detected In the pulse width measurement mode the count value of the 16 bit cou...

Page 147: ...e used only as a capture register In any other mode this register can be used only as a compare register The TP0CCR1 register can be read or written during operation This register can be read or writt...

Page 148: ...easurement mode the count value of the 16 bit counter is stored in the TP0CCR1 register and the 16 bit counter is cleared 0000H if the valid edge of the capture trigger input pin TIP01 pin is detected...

Page 149: ...ared to 0000H when the TP0CE bit 0 If the TP0CNT register is read at this time the value of the 16 bit counter FFFFH is not read but 0000H is read Reset sets the TP0CE bit to 0 Therefore the TP0CNT re...

Page 150: ...tch write One shot pulse output mode Note 2 Valid Valid Compare only Anytime write PWM output mode Invalid Invalid Compare only Batch write Free running timer mode Invalid Invalid Switching enabled An...

Page 151: ...erval can be output from the TOP00 pin Usually the TP0CCR1 register is not used in the interval timer mode Figure 6 2 Configuration of Interval Timer 16 bit counter Output controller CCR0 buffer regis...

Page 152: ...lculated by the following expression Interval Set value of TP0CCR0 register 1 Count clock cycle Figure 6 4 Register Setting for Interval Timer Mode Operation 1 2 a TMP0 control register 0 TP0CTL0 0 1...

Page 153: ...can be read e TMP0 capture compare register 0 TP0CCR0 If the TP0CCR0 register is set to D0 the interval is as follows Interval D0 1 Count clock cycle f TMP0 capture compare register 1 TP0CCR1 Usually...

Page 154: ...2 TP0CE bit 1 TP0CE bit 0 Register initial setting TP0CTL0 register TP0CKS0 to TP0CKS2 bits TP0CTL1 register TP0IOC0 register TP0CCR0 register Initial setting of these registers is performed before se...

Page 155: ...r is cleared to 0000H the INTTP0CC0 signal is generated at each count clock and the output of the TOP00 pin is inverted The value of the 16 bit counter is always 0000H Count clock 16 bit counter TP0CE...

Page 156: ...n with the next count up timing The INTTP0CC0 signal is generated and the output of the TOP00 pin is inverted At this time an overflow interrupt request signal INTTP0OV is not generated nor is the ove...

Page 157: ...cle Interval time 2 D2 1 Count clock cycle If the value of the TP0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1 the count value is transferred to the...

Page 158: ...register Figure 6 6 Configuration of TP0CCR1 Register CCR0 buffer register TP0CCR0 register TP0CCR1 register CCR1 buffer register TOP00 pin INTTP0CC0 signal TOP01 pin INTTP0CC1 signal 16 bit counter O...

Page 159: ...is generated once per cycle At the same time the output of the TOP01 pin is inverted The TOP01 pin outputs a square wave with the same cycle as that output by the TOP00 pin Figure 6 7 Timing Chart Whe...

Page 160: ...unt value of the 16 bit counter does not match the value of the TP0CCR1 register Consequently the INTTP0CC1 signal is not generated nor is the output of the TOP01 pin changed Figure 6 8 Timing Chart W...

Page 161: ...mode Figure 6 9 Configuration in External Event Count Mode 16 bit counter CCR0 buffer register TP0CE bit TP0CCR0 register Edge detector Clear Match signal INTTP0CC0 signal TIP00 pin external event co...

Page 162: ...0CC0 signal is generated each time the valid edge of the external event count input has been detected set value of TP0CCR0 register 1 times Figure 6 11 Register Setting for Operation in External Event...

Page 163: ...C0 is generated when the number of external event counts reaches D0 1 g TMP0 capture compare register 1 TP0CCR1 Usually the TP0CCR1 register is not used in the external event count mode However the se...

Page 164: ...it 1 TP0CE bit 0 Register initial setting TP0CTL0 register TP0CKS0 to TP0CKS2 bits TP0CTL1 register TP0IOC0 register TP0IOC2 register TP0CCR0 register Initial setting of these registers is performed b...

Page 165: ...or the count clock TP0CTL1 TP0MD2 to TP0CTL1 TP0MD0 bits 000 TP0CTL1 TP0EEE bit 1 a Operation if TP0CCR0 register is set to FFFFH If the TP0CCR0 register is set to FFFFH the 16 bit counter counts to F...

Page 166: ...ernal event count signal interval 2 D2 1 If the value of the TP0CCR0 register is changed from D1 to D2 while the count value is greater than D2 but less than D1 the count value is transferred to the C...

Page 167: ...R1 buffer register Clear Match signal Match signal INTTP0CC0 signal INTTP0CC1 signal Edge detector TIP00 pin If the set value of the TP0CCR1 register is smaller than the set value of the TP0CCR0 regis...

Page 168: ...et value of the TP0CCR0 register the INTTP0CC1 signal is not generated because the count value of the 16 bit counter and the value of the TP0CCR1 register do not match Figure 6 15 Timing Chart When D0...

Page 169: ...can also be output by generating a software trigger instead of using the external trigger When using a software trigger a square wave that has one cycle of the PWM waveform as half its cycle can also...

Page 170: ...high level regardless of the status high low when a trigger occurs The active level width cycle and duty factor of the PWM waveform can be calculated as follows Active level width Set value of TP0CCR...

Page 171: ...P0CKS0 to TP0CKS2 bits 1 Count with external event input signal Generate software trigger when 1 is written 0 1 0 TP0MD2 TP0MD1 TP0MD0 TP0EEE TP0EST 0 1 0 External trigger pulse output mode c TMP0 I O...

Page 172: ...0ETS0 TP0EES1 e TMP0 counter read buffer register TP0CNT The value of the 16 bit counter can be read by reading the TP0CNT register f TMP0 capture compare registers 0 and 1 TP0CCR0 and TP0CCR1 If D0 i...

Page 173: ...rigger Pulse Output Mode 1 2 FFFFH 16 bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TP0CCR1 register CCR1 buffer register INTTP0CC1 signal TOP01 pin output Externa...

Page 174: ...d When the counter is cleared after setting the value of the TP0CCRa register is transferred to the CCRa buffer register START Setting of TP0CCR1 register 1 Count operation start flow 2 TP0CCR0 and TP...

Page 175: ...e the TP0CCR1 register last Rewrite the TP0CCRa register after writing the TP0CCR1 register after the INTTP0CC0 signal is detected FFFFH 16 bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer reg...

Page 176: ...gister To change only the active level width duty factor of the PWM waveform only the TP0CCR1 register has to be set After data is written to the TP0CCR1 register the value written to the TP0CCRa regi...

Page 177: ...egister TP0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D0 0000H D0 0000H D0 0000H D0 1 D0 0000 FFFF 0000 D0 1 D0 0000 0001 To output a 100 waveform set a value of set value of TP0...

Page 178: ...eform is shortened 16 bit counter TP0CCR1 register INTTP0CC1 signal TOP01 pin output External trigger input TIP00 pin input D1 D1 1 0000 FFFF 0000 Shortened If the trigger is detected immediately befo...

Page 179: ...o trigger detection 16 bit counter TP0CCR0 register INTTP0CC0 signal TOP01 pin output External trigger input TIP00 pin input D0 D0 1 D0 0000 FFFF 0000 0000 Extended If the trigger is detected immediat...

Page 180: ...nt value of the 16 bit counter matches the value of the TP0CCR1 register Count clock 16 bit counter TP0CCR1 register TOP01 pin output INTTP0CC1 signal D1 D1 2 D1 1 D1 D1 1 D1 2 Usually the INTTP0CC1 s...

Page 181: ...ware trigger can also be generated to output the pulse When the software trigger is used the TOP00 pin outputs the active level while the 16 bit counter is counting and the inactive level when the cou...

Page 182: ...ne shot pulse is output the 16 bit counter is set to FFFFH stops counting and waits for a trigger If a trigger is generated again while the one shot pulse is being output it is ignored The output dela...

Page 183: ...y TP0CKS0 to TP0CKS2 bits 1 Count external event input signal Generate software trigger when 1 is written 0 1 1 TP0MD2 TP0MD1 TP0MD0 TP0EEE TP0EST 0 1 1 One shot pulse output mode c TMP0 I O control r...

Page 184: ...MP0 counter read buffer register TP0CNT The value of the 16 bit counter can be read by reading the TP0CNT register f TMP0 capture compare registers 0 and 1 TP0CCR0 and TP0CCR1 If D0 is set to the TP0C...

Page 185: ...ter TP0IOC2 register TP0CCR0 register TP0CCR1 register Initial setting of these registers is performed before setting the TP0CE bit to 1 The TP0CKS0 to TP0CKS2 bits can be set at the same time when co...

Page 186: ...OP00 pin output software trigger When the TP0CCR0 register is rewritten from D00 to D01 and the TP0CCR1 register from D10 to D11 where D00 D01 and D10 D11 if the TP0CCR1 register is rewritten when the...

Page 187: ...ed when the count value of the 16 bit counter matches the value of the TP0CCR1 register Count clock 16 bit counter TP0CCR1 register TOP01 pin output INTTP0CC1 signal D1 D1 2 D1 1 D1 D1 1 D1 2 Usually...

Page 188: ...dition a pulse with one cycle of the PWM waveform as half its cycle is output from the TOP00 pin Figure 6 24 Configuration in PWM Output Mode CCR0 buffer register TP0CE bit TP0CCR0 register 16 bit cou...

Page 189: ...ster 1 Count clock cycle Duty factor Set value of TP0CCR1 register Set value of TP0CCR0 register 1 The PWM waveform can be changed by rewriting the TP0CCRa register while the counter is operating The...

Page 190: ...0MD0 TP0EEE TP0EST 1 0 0 PWM output mode 0 Operate on count clock selected by TP0CKS0 to TP0CKS2 bits 1 Count with external event count input signal c TMP0 I O control register 0 TP0IOC0 0 0 0 0 0 1 T...

Page 191: ...er read buffer register TP0CNT The value of the 16 bit counter can be read by reading the TP0CNT register f TMP0 capture compare registers 0 and 1 TP0CCR0 and TP0CCR1 If D0 is set to the TP0CCR0 regis...

Page 192: ...rocessing Flow in PWM Output Mode 1 2 FFFFH 16 bit counter 0000H TP0CE bit TP0CCR0 register CCR0 buffer register INTTP0CC0 signal TOP00 pin output TP0CCR1 register CCR1 buffer register INTTP0CC1 signa...

Page 193: ...s cleared after setting the value of the TP0CCRa register is transferred to the CCRa buffer register START Setting of TP0CCR1 register 1 Count operation start flow 2 TP0CCR0 TP0CCR1 register setting c...

Page 194: ...irst set the cycle to the TP0CCR0 register and then set the active level width to the TP0CCR1 register To change only the cycle of the PWM waveform first set the cycle to the TP0CCR0 register and then...

Page 195: ...0CCR1 register INTTP0CC0 signal INTTP0CC1 signal TOP01 pin output D00 0000H D00 0000H D00 0000H D00 1 D00 0000 FFFF 0000 D00 1 D00 0000 0001 To output a 100 waveform set a value of set value of TP0CCR...

Page 196: ...t value of the 16 bit counter matches the value of the TP0CCR1 register Count clock 16 bit counter TP0CCR1 register TOP01 pin output INTTP0CC1 signal D1 D1 2 D1 1 D1 D1 1 D1 2 Usually the INTTP0CC1 si...

Page 197: ...CS1 bits Figure 6 28 Configuration in Free Running Timer Mode TP0CCR0 register capture TP0CE bit TP0CCR1 register capture 16 bit counter TP0CCR1 register compare TP0CCR0 register compare Output contro...

Page 198: ...t the next clock is cleared to 0000H and continues counting At this time the overflow flag TP0OPT0 TP0OVF bit is also set to 1 Clear the overflow flag to 0 by executing the CLR instruction by software...

Page 199: ...tes an overflow interrupt request signal INTTP0OV at the next clock is cleared to 0000H and continues counting At this time the overflow flag TP0OPT0 TP0OVF bit is also set to 1 Clear the overflow fla...

Page 200: ...0CTL1 0 0 0 1 0 0 TP0CTL1 1 0 1 TP0MD2 TP0MD1 TP0MD0 TP0EEE TP0EST 1 0 1 Free running mode 0 Operate with count clock selected by TP0CKS0 to TP0CKS2 bits 1 Count on external event count input signal c...

Page 201: ...register Specifies if TP0CCR1 register functions as capture or compare register 0 0 0 1 TP0CCS0 TP0OVF TP0CCS1 g TMP0 counter read buffer register TP0CNT The value of the 16 bit counter can be read b...

Page 202: ...ware Processing Flow in Free Running Timer Mode Compare Function 1 2 FFFFH 16 bit counter 0000H TP0CE bit TP0CCR0 register INTTP0CC0 signal TOP00 pin output TP0CCR1 register INTTP0CC1 signal TOP01 pin...

Page 203: ...gister TP0IOC2 register TP0OPT0 register TP0CCR0 register TP0CCR1 register Initial setting of these registers is performed before setting the TP0CE bit to 1 The TP0CKS0 to TP0CKS2 bits can be set at t...

Page 204: ...Flow in Free Running Timer Mode Capture Function 1 2 FFFFH 16 bit counter 0000H TP0CE bit TIP00 pin input TP0CCR0 register INTTP0CC0 signal TIP01 pin input TP0CCR1 register INTTP0CC1 signal INTTP0OV s...

Page 205: ...0CTL1 register TP0IOC1 register TP0OPT0 register Initial setting of these registers is performed before setting the TP0CE bit to 1 The TP0CKS0 to TP0CKS2 bits can be set at the same time when counting...

Page 206: ...al period 10000H D11 D10 Interval period 10000H D12 D11 Interval period 10000H D13 D12 Interval period D00 1 Interval period 10000H D01 D00 Interval period D02 D01 Interval period 10000H D03 D02 Inter...

Page 207: ...D00 D11 D01 D12 D04 D13 D02 D03 D10 0000H D11 D12 D13 Pulse interval D00 Pulse interval 10000H D01 D00 Pulse interval D02 D01 Pulse interval 10000H D03 D02 Pulse interval 10000H D04 D03 Pulse interva...

Page 208: ...ee running timer mode 1 Read the TP0CCR0 register setting of the default value of the TIP00 pin input 2 Read the TP0CCR1 register setting of the default value of the TIP01 pin input 3 Read the TP0CCR0...

Page 209: ...default value of the TIP00 pin input 2 Read the TP0CCR1 register setting of the default value of the TIP01 pin input 3 An overflow occurs Set the TP0OVF0 and TP0OVF1 flags to 1 in the overflow interr...

Page 210: ...tting of the default value of the TIP00 pin input 2 Read the TP0CCR1 register setting of the default value of the TIP01 pin input 3 An overflow occurs Nothing is done by software 4 Read the TP0CCR0 re...

Page 211: ...ay occur when long pulse width is measured in the free running timer mode 1 Read the TP0CCRa register setting of the default value of the TIP0a pin input 2 An overflow occurs Nothing is done by softwa...

Page 212: ...1 Read the TP0CCRa register setting of the default value of the TIP0a pin input 2 An overflow occurs Increment the overflow counter and clear the overflow flag to 0 in the overflow interrupt servicing...

Page 213: ...ignal Overflow flag TP0OVF bit Read Write 0 write signal Overflow set signal Register access signal Overflow flag TP0OVF bit Read Write 0 write signal Overflow set signal 0 write signal Overflow set s...

Page 214: ...01 pin as the capture trigger input pin Specify No edge detected by using the TP0IOC1 register for the unused pins When an external clock is used as the count clock measure the pulse width of the TIP0...

Page 215: ...ter is cleared to 0000H and a capture interrupt request signal INTTP0CCa is generated The pulse width is calculated as follows Pulse width Captured value Count clock cycle If the valid edge is not inp...

Page 216: ...control register 1 TP0CTL1 0 0 0 1 0 0 TP0CTL1 1 1 0 TP0MD2 TP0MD1 TP0MD0 TP0EEE TP0EST 1 1 0 Pulse width measurement mode 0 Operate with count clock selected by TP0CKS0 to TP0CKS2 bits 1 Count extern...

Page 217: ...CCS0 TP0OVF TP0CCS1 f TMP0 counter read buffer register TP0CNT The value of the 16 bit counter can be read by reading the TP0CNT register g TMP0 capture compare registers 0 and 1 TP0CCR0 and TP0CCR1 T...

Page 218: ...TP0CTL1 register TP0IOC1 register TP0IOC2 register TP0OPT0 register Initial setting of these registers is performed before setting the TP0CE bit to 1 The TP0CKS0 to TP0CKS2 bits can be set at the sam...

Page 219: ...signal Register access signal Overflow flag TP0OVF bit Read Write 0 write signal Overflow set signal Register access signal Overflow flag TP0OVF bit Read Write 0 write signal Overflow set signal 0 wr...

Page 220: ...One shot pulse output mode One shot pulse output PWM output mode PWM output Square wave output Free running timer mode Square wave output only when compare function is used Pulse width measurement mo...

Page 221: ...PaNFC PaNFC2 to PaNFC PaNFC0 bits 1 TIP0a noise elimination control register PaNFC This register is used to select the sampling clock and the number of times of sampling for eliminating digital noise...

Page 222: ...e mode or the valid edge of the capture trigger 4 Enable the TMP0 count operation Noise elimination width The digital noise elimination width tWTIP0a is as follows where T is the sampling clock period...

Page 223: ...ptured in the TP0CCRn register if the capture trigger is input immediately after the TP0CE bit is set to 1 a Free running timer mode Count clock 0000H FFFFH TP0CE bit TP0CCR0 register FFFFH 0001H 0000...

Page 224: ...vent counter 01 can output a square wave with any selected frequency 3 External event counter 16 bit timer event counter 01 can measure the number of pulses of an externally input signal 4 One shot pu...

Page 225: ...11 and TO01 pin functions refer to Table 4 12 Settings When Port Pins Are Used for Alternate Functions The block diagram is shown below Figure 7 1 Block Diagram of 16 Bit Timer Event Counter 01 INTTM0...

Page 226: ...3 and TMC01 TMC012 bits are other than 00 The value of the TM01 register is 0000H if it is read when the TMC013 and TMC012 bits are 00 The count value is reset to 0000H in the following cases At reset...

Page 227: ...ation These registers can be read or written in 16 bit units Reset sets these registers to 0000H a 16 bit timer capture compare register 010 CR010 CR010 12 10 8 6 4 2 After reset 0000H R W Address FFF...

Page 228: ...g a capture trigger The valid edge of the TI010 pin can be selected as the capture trigger The valid edge of the TI010 pin is set with the PRM01 register Cautions 1 When the P35 pin is used as the val...

Page 229: ...the timer operation does not occur and timer output is not changed and the first match timing is as follows A match interrupt occurs at the timing when the timer counter TM01 register is changed from...

Page 230: ...Position of edge to be captured 01 Rising 00 Falling TI010 pin input Note 11 Both edges Capture operation of CR011 register Interrupt signal INTTM011 signal is generated each time value is captured N...

Page 231: ...g and detects an overflow Rewriting TMC01 is prohibited during operation when the TMC013 and TMC012 bits other than 00 However it can be changed when the TMC013 and TMC012 bits are cleared to 00 stopp...

Page 232: ...01 0 Match between TM01 and CR010 or match between TM01 and CR011 1 Match between TM01 and CR010 or match between TM01 and CR011 Trigger input of TI010 pin valid edge OVF01 TM01 register overflow flag...

Page 233: ...on 0 Captures on valid edge of TI011 pin 1 Captures on valid edge of TI010 pin by reverse phase Note The valid edge of the TI011 and TI010 pin is set by the PRM01 register If PRM01 ES101 and PRM01 ES1...

Page 234: ...OC011 bits to 1 2 Set only the TOE01 bit to 1 3 Set either the LVS01 bit or the LVR01 bit to 1 1 2 After reset 00H R W Address FFFFF619H 7 6 5 4 3 2 1 0 TOC01 0 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011...

Page 235: ...01 1 The LVS01 LVR01 and TOE01 bits being simultaneously set to 1 is prohibited The LVS01 and LVR01 bits are trigger bits By setting these bits to 1 the initial value of the output level of the TO01 p...

Page 236: ...ation of the 16 bit timer event counter 01 is enabled when the TI010 or TI011 pin is at high level and when the valid edge of the TI010 or TI011 pin is specified to be the rising edge or both edges th...

Page 237: ...r 01 The count clock for 16 bit timer event counter 01 is set by using the PRM01 PRM011 PRM01 PRM010 and SELCNT1 ISEL11 bits in combination SELCNT1 Register PRM01 Register Selection of Count Clock Not...

Page 238: ...This INTTM010 signal enables the TM01 register to operate as an interval timer Remarks 1 For the alternate function pin settings refer to Table 4 12 Settings When Port Pins Are Used for Alternate Fun...

Page 239: ...ation control register 1 SELCNT1 0 PRM01 0 0 0 0 PRM011 PRM010 SELCNT1 ES111 ES110 ES101 ES100 Selects count clock 0 0 1 0 1 ISEL11 0 1 e 16 bit timer counter 01 TM01 By reading the TM01 register the...

Page 240: ...11 00 00 N N N 1 2 TMC013 TMC012 bits 11 TMC013 TMC012 bits 00 Register initial setting PRM01 register SELCNT1 register CRC01 register CR010 register port setting Initial setting of these registers i...

Page 241: ...nal INTTM010 is generated and output of the TO01 pin is inverted This TO01 pin output that is inverted at fixed intervals enables TO01 to output a square wave Remarks 1 For the alternate function pin...

Page 242: ...output F F 0 1 1 1 d Prescaler mode register 01 PRM01 selector operation control register 1 SELCNT1 0 PRM01 0 0 0 0 PRM011 PRM010 SELCNT1 ES111 ES110 ES101 ES100 Selects count clock 0 0 1 0 1 ISEL11 0...

Page 243: ...TMC012 bits 00 Register initial setting PRM01 register SELCNT1 register CRC01 register TOC01 registerNote CR010 register port setting Initial setting of these registers is performed before setting th...

Page 244: ...of times of detection of valid edge of external event Set value of the CR010 register 1 However the first match interrupt immediately after the timer event counter has started operating is generated w...

Page 245: ...rts TO01 output on match between TM01 and CR010 CR011 Specifies initial value of TO01 output F F 0 1 0 1 0 1 d Prescaler mode register 01 PRM01 selector operation control register 1 SELCNT1 0 PRM01 0...

Page 246: ...egister initial setting PRM01 register SELCNT1 register CRC01 register TOC01 registerNote CR010 register port setting Initial setting of these registers is performed before setting the TMC013 and TMC0...

Page 247: ...11 registers are used as compare registers Signals INTTM010 and INTTM011 are generated when the value of the TM01 register matches the value of the CR010 and CR011 registers b When the CR010 and CR011...

Page 248: ...egister Figure 7 13 Block Diagram of Clear Start Mode Entered by TI010 Pin Valid Edge Input CR010 register Compare Register CR011 register Compare Register 16 bit counter TM01 Clear Output controller...

Page 249: ...11 TO01 pin output M 10 M N N N N M M M 00 N b TOC01 13H PRM01 10H CRC01 00H TMC01 0AH TM01 register 0000H Operable bits TMC013 TMC012 Count clear input TI010 pin input Compare register CR010 Compare...

Page 250: ...gister Figure 7 15 Block Diagram of Clear Start Mode Entered by TI010 Pin Valid Edge Input CR010 Register Compare Register CR011 Register Capture Register 16 bit counter TM01 Clear Output controller E...

Page 251: ...register CR010 Compare match interrupt INTTM010 Capture register CR011 Capture interrupt INTTM011 TO01 pin output 0000H 10 Q P N M S 00 0000H M N S P Q This is an application example where the output...

Page 252: ...011 TO01 pin output 0003H 0003H 10 Q P N M S 00 0000H M 4 4 4 4 N S P Q This is an application example where the width set to the CR010 register 4 clocks in this example is to be output from the TO01...

Page 253: ...gister Figure 7 17 Block Diagram of Clear Start Mode Entered by TI010 Pin Valid Edge Input CR010 Register Capture Register CR011 Register Compare Register 16 bit counter TM01 Clear Output controller E...

Page 254: ...interrupt INTTM011 TO01 pin output This is an application example where the output level of the TO01 pin is to be inverted when the count value has been captured cleared The TM01 register is cleared...

Page 255: ...is to be output from the TO01 pin when the count value has been captured cleared The TM01 register is cleared to 0000H at the rising edge detection of the TI010 pin and captured to the CR010 register...

Page 256: ...011 pin Selector Figure 7 20 Timing Example of Clear Start Mode Entered by TI010 Pin Valid Edge Input CR010 Register Capture Register CR011 Register Capture Register 1 3 a TOC01 13H PRM01 30H CRC01 05...

Page 257: ...011 pin input Capture register CR010 Capture interrupt INTTM010 Capture count clear input TI010 Capture register CR011 Capture interrupt INTTM011 TO01 pin output 10 R S T O L M N P Q 00 FFFFH L L L 00...

Page 258: ...the CR010 register in the phase reverse to the falling edge of the TI010 pin i e rising edge and to the CR011 register at the falling edge of the TI010 pin The high and low level widths of the input...

Page 259: ...1 CRC012 CRC011 CRC010 0 CR010 used as compare register 1 CR010 used as capture register 0 CR011 used as compare register 1 CR011 used as capture register 0 TI011 pin is used as capture trigger of CR...

Page 260: ...compare register 010 CR010 When this register is used as a compare register and when its value matches the count value of the TM01 register an interrupt signal INTTM010 is generated The count value o...

Page 261: ...setting PRM01 register SELCNT1 register CRC01 register TOC01 registerNote CR010 CR011 registers TMC01 TMC011 bit port setting Initial setting of these registers is performed before setting the TMC013...

Page 262: ...ther the CR010 register or CR011 register is used as a compare register and the other is used as a capture register Both the CR010 and CR011 registers are used as capture registers Remarks 1 For the a...

Page 263: ...o compare registers are used in the free running timer mode The output level of the TO01 pin is reversed each time the count value of the TM01 register matches the set values of the CR010 and CR011 re...

Page 264: ...ture interrupt INTTM011 TO01 pin output Overflow flag OVF01 0 write clear 0 write clear 0 write clear 0 write clear This is an application example where a compare register and a capture register are u...

Page 265: ...TM01 Capture register CR010 Capture signal Capture signal Interrupt signal INTTM011 Interrupt signal INTTM010 Capture register CR011 Operable bits TMC013 TMC012 Count clock Edge detection TI010 pin Ed...

Page 266: ...register CR011 Capture interrupt INTTM011 Capture trigger input TI011 Capture register CR010 Capture interrupt INTTM010 Overflow flag OVF01 0 write clear 0 write clear 0 write clear 0 write clear Thi...

Page 267: ...ter CR010 Capture interrupt INTTM010 Capture trigger input TI010 Capture register CR011 Capture interrupt INTTM011 01 L M P S N O R Q T 00 0000H 0000H L M N O P Q R S T L L This is an application exam...

Page 268: ...CR010 used as compare register 1 CR010 used as capture register 0 CR011 used as compare register 1 CR011 used as capture register 0 TI011 pin is used as capture trigger of CR010 1 Reverse phase of TI...

Page 269: ...r 010 CR010 When this register is used as a compare register and when its value matches the count value of the TM01 register an interrupt signal INTTM010 is generated The count value of the TM01 regis...

Page 270: ...C013 TMC012 bits 0 1 Register initial setting PRM01 register SELCNT1 register CRC01 register TOC01 registerNote CR010 CR011 register TMC01 TMC011 bit port setting Initial setting of these registers is...

Page 271: ...gister 1 Count clock cycle Duty Set value of the CR011 register 1 Set value of the CR010 register 1 Caution To change the duty factor value of the CR011 register during operation refer to 7 5 1 Rewrit...

Page 272: ...R011 00 Disables one shot pulse output Specifies initial value of TO01 output F F 0 1 1 1 d Prescaler mode register 01 PRM01 selector operation control register 1 SELCNT1 0 PRM01 0 0 0 0 PRM011 PRM010...

Page 273: ...tial setting PRM01 register SELCNT1 register CRC01 register TOC01 registerNote CR010 CR011 registers port setting Initial setting of these registers is performed before setting the TMC013 and TMC012 b...

Page 274: ...on Do not input the trigger again setting OSPT01 to 1 or detecting the valid edge of the TI010 pin while the one shot pulse is output To output the one shot pulse again generate the trigger after the...

Page 275: ...as compare register CR011 used as compare register c 16 bit timer output control register 01 TOC01 0 0 1 1 1 0 1 LVR01 LVS01 TOC014 OSPE01 OSPT01 TOC011 TOE01 Enables TO01 pin output Inverts TO01 out...

Page 276: ...sed as a compare register when a one shot pulse is output When the value of the TM01 register matches that of the CR010 register an interrupt signal INTTM010 is generated and the output level of the T...

Page 277: ...TI010 pin Overflow plug OVF01 Compare register CR010 Compare match interrupt INTTM010 Compare register CR011 Compare match interrupt INTTM011 TO01 pin output TO01 output control bits TOE01 TOC014 TOC...

Page 278: ...sters is performed before setting the TMC013 and TMC012 bits Starts count operation START 1 Count operation start flow 2 One shot trigger input flow TMC013 TMC012 bits 00 The counter is initialized an...

Page 279: ...1 flag If it is set to 1 clear it to 0 by software Figure 7 37 Block Diagram of Pulse Width Measurement Free Running Timer Mode 16 bit counter TM01 Capture register CR010 Capture signal Capture signal...

Page 280: ...captured to the CR011 register When the valid edge of the TI011 pin is detected the count value of the TM01 register is captured to the CR010 register Specify detection of both the edges of the TI010...

Page 281: ...ve to be saved By subtracting the value of one capture register from that of another a high level width low level width and cycle are calculated If an overflow occurs the value becomes negative if one...

Page 282: ...erflow If an overflow occurs take the value that results from adding 10000H to the value stored in the CR011 register as a cycle Clear the TMC01 OVF01 bit to 0 Figure 7 41 Timing Example of Pulse Widt...

Page 283: ...011 pin is used as capture trigger of CR010 1 Reverse phase of TI010 pin is used as capture trigger of CR010 c 16 bit timer output control register 01 TOC01 0 0 0 0 0 LVR01 LVS01 TOC014 OSPE01 OSPT01...

Page 284: ...is register is used as a capture register Either the TI010 or TI011 pin is selected as a capture trigger When a specified edge of the capture trigger is detected the count value of the TM01 register i...

Page 285: ...ger input TI011 Capture register CR010 Capture interrupt INTTM010 01 D00 D00 D01 D01 D02 D02 D03 D03 D04 D04 D10 D10 D11 D11 D12 D12 D13 D13 00 00 0000H 0000H 1 2 2 2 2 2 2 2 2 2 3 b Example of clear...

Page 286: ...r 10 Register initial setting PRM01 register SELCNT1 register CRC01 register port setting Initial setting of these registers is performed before setting the TMC013 and TMC012 bits Starts count operati...

Page 287: ...11 bit 1 2 Disable reversal of the timer output when the value of the TM01 register matches that of the CR011 register TOC01 TOC014 bit 0 3 Change the value of the CR011 register 4 Wait for one cycle...

Page 288: ...Bits TOC01 LVS01 bit TOC01 LVR01 bit Operable bits TMC013 TMC012 TO01 pin output INTTM010 signal 1 00 2 1 3 4 4 4 01 10 or 11 1 The TO01 pin output goes high when the LVS01 and LVR01 bits 10 2 The TO...

Page 289: ...TI010 pin input use the output of the TO01 pin that functions alternately as P32 When using the output of the TO01 pin that functions alternately as P35 the TI010 pin that functions alternately as P3...

Page 290: ...se TM01 count value Edge input INTTM011 Value captured to CR011 Capture read signal Capture operation is performed but read value is not guaranteed Capture operation b The values of the CR010 and CR01...

Page 291: ...ter Figure 7 48 Operation Timing of OVF01 Flag FFFEH FFFFH FFFFH 0000H 0001H Count pulse TM01 INTTM010 OVF01 CR010 b Clearing of OVF01 flag After the TM01 register overflows clearing OVF01 flag is inv...

Page 292: ...11 pin during this operation the capture operation is not performed but the INTTM010 signal is generated as an external interrupt signal Mask the INTTM010 signal when the external interrupt is not use...

Page 293: ...Mode using 8 bit timer event counter alone individual mode 8 bit timer event counter 5n operates as an 8 bit timer event counter The following functions can be used Interval timer External event count...

Page 294: ...TMC50 TMC51 16 bit timer mode control register 5 TMC5 Only when using cascade connection Note When using the functions of the TI5n and TO5n pins refer to Table 4 12 Settings When Port Pins Are Used f...

Page 295: ...rs can be read only in 16 bit units Therefore read these registers twice and compare the values taking into consideration that the reading occurs during a count change TM5n n 0 1 6 4 2 After reset 00H...

Page 296: ...0H to FFH When using the TM50 register and TM51 register in cascade as a 16 bit timer the CR50 register and CR51 register operate as 16 bit timer compare register 5 CR5 The counter value and register...

Page 297: ...units Reset sets this register to 00H Falling edge of TI5n Rising edge of TI5n fXX fXX 2 fXX 4 fXX 64 fXX 256 INTTM010 Count clock selectionNote TCL5n2 0 0 0 0 1 1 1 1 TCL5n1 0 0 1 1 0 0 1 1 TCL5n0 0...

Page 298: ...by the TM5n register Selects the operation mode of the TM5n register Selects the individual mode or cascade connection mode Sets the status of the timer output flip flop Controls the timer output flip...

Page 299: ...peration Enable inversion operation High active Low active TMC5n1 0 1 Other than PWM free running timer mode TMC5n6 bit 0 Controls timer F F PWM free running timer mode TMC5n6 bit 1 Selects active lev...

Page 300: ...on and selects the mode in which clear start occurs on a match between the TM5n register and CR5n register TMC5n register 0000xx00B don t care 2 When the TMC5n TCE5n bit is set to 1 the count operatio...

Page 301: ...2 When CR5n register 00H t Interval time 00H 00H 00H 00H 00H Count clock TM5n count value CR5n TCE5n INTTM5n Remark n 0 1 When CR5n register FFH t 01H 00H FEH FFH 00H FEH FFH 00H FFH FFH FFH Count cl...

Page 302: ...s the mode in which clear start occurs on a match between the TM5n register and CR5n register disables timer output F F inversion operation and disables timer output TMC5n register 0000xx00B don t car...

Page 303: ...ode in which clear start occurs on a match between the TM5n register and CR5n register sets initial value of timer output enables timer output F F inversion operation and enables timer output TMC5n re...

Page 304: ...ion t Interval time Interval time 00H N 01H 01H 00H N N N N N N 01H 00H Clear Interrupt acknowledgment Interrupt acknowledgment Clear Count clock TM5n count value CR5n TO5nNote TCE5n INTTM5n Count sta...

Page 305: ...01000001B or 01000011B For the alternate function pin settings refer to Table 4 12 Settings When Port Pins Are Used for Alternate Functions 2 When the TMC5n TCE5n bit is set to 1 counting starts PWM...

Page 306: ...Active level Count clock TM5n count value CR5n TCE5n INTTM5n TO5n t When CR5n register 00H 00H N 1N 2 N 00H 00H M 00H FFH 01H 02H 01H 00H FFH 02H 01H Inactive level Inactive level Count clock TM5n co...

Page 307: ...tion N M M M 1M 2 M M 1M 2 FFH 02H 00H 01H FFH 02H 00H 01H Count clock TM5n count value CR5n TCE5n H INTTM5n TO5n 2 t When the value of the CR5n register changes from N to M after the rising edge of t...

Page 308: ...TMC50 register 0000xx00B TMC51 register 0001xx00B 2 Set the TMC51 TCE51 bit to 1 Then set the TMC50 TCE50 bit to 1 to start the count operation 3 When the values of the TM5 register and CR5 register...

Page 309: ...6 bit resolution Figure 8 7 Cascade Connection Mode with 16 Bit Resolution 00H N 1 01H 00H FFH 00H 01H FFH 00H FFH M 1 01H 00H 00H N A 01H 00H 02H M 00H 00H B N N M Interval time Operation enabled cou...

Page 310: ...ttings refer to Table 4 12 Settings When Port Pins Are Used for Alternate Functions 2 Set the TMC51 TCE51 bit to 1 Then set the TMC50 TCE50 bit to 1 and count the number of pulses input from the TI50...

Page 311: ...occurs on a match between the TM5 register and CR5 register LVS50 LVR50 Timer Output F F Status Settings 1 0 High level output 0 1 Low level output Enables timer output F F inversion and enables time...

Page 312: ...mer An error of up to 1 clock occurs before the match signal is generated after the timer has been started This is because the TM5n register is started asynchronously to the count pulse Figure 8 8 Cou...

Page 313: ...following hardware Table 9 1 Configuration of 8 Bit Timer Hn Item Configuration Timer registers 8 bit timer counter Hn 1 each Registers 8 bit timer H compare register n0 CMPn0 1 each 8 bit timer H com...

Page 314: ...ode register n TMHMDn 8 bit timer H carrier control register n TMCYCn Note fXX 2 10 when n 0 fR 2 11 when n 1 Remark n 0 1 1 8 bit timer H compare register n0 CMPn0 This CMPn0 register can be read or...

Page 315: ...alue of the CMPn1 register is changed to the new value If matching of the count value and the CMPn1 register value and writing a value to the CMPn1 register conflict the value of the CMPn1 register is...

Page 316: ...imer H carrier control register n TMCYCn Remarks 1 To use the TOHn pin function refer to Table 4 12 Settings When Port Pins Are Used for Alternate Functions 2 n 0 1 1 8 bit timer H mode register n TMH...

Page 317: ...OLEV0 0 1 Timer output level control default Disable output Enable output TOEN0 0 1 Timer output control fXX 16 0 MHz 7 6 5 4 3 2 1 0 Setting prohibited fXX 10 0 MHz Setting prohibited 100 ns 200 ns 8...

Page 318: ...Low level High level TOLEV1 0 1 Timer output level control default Disable output Enable output TOEN1 0 1 Timer output control fXX 16 0 MHz 7 6 5 4 3 2 1 0 Setting prohibited 100 ns 200 ns 800 ns 3 2...

Page 319: ...in 8 bit or 1 bit units The NRZn bit is a read only bit Reset sets this register to 00H 0 TMCYCn n 0 1 0 0 0 0 RMCn NRZBn NRZn After reset 00H R W Address TMCYC0 FFFFF581H TMCYC1 FFFFF591H Low level o...

Page 320: ...When Port Pins Are Used for Alternate Functions 2 For INTTMHn interrupt enable refer to CHAPTER 17 INTERRUPT EXCEPTION PROCESSING FUNCTION Setting 1 Set each register Figure 9 2 Register Settings in...

Page 321: ...the TMHEn bit is set to 1 the count operation is enabled The count clock starts counting no more than one clock after operation has been enabled 2 When the count value of 8 bit timer counter Hn and th...

Page 322: ...ster FFH 00H CMPn0 TMHEn INTTMHn TOHn 01H FEH FFH 00H FEH FFH 00H FFH Interval time Count clock Count start Clear Clear 8 bit timer counter Hn count value Operation when CMPn0 register 00H Count clock...

Page 323: ...e of 8 bit timer counter Hn and the set value of the CMPn1 register match the TOHn output level is inverted Remarks 1 For the alternate function pin TOHn settings refer to Table 4 12 Settings When Por...

Page 324: ...of any duty can be obtained through the repetition of steps 3 and 4 above 6 To stop the count operation clear the TMHEn bit to 0 Designating the set value of the CMPn0 register as N the set value of...

Page 325: ...t level 2 When the count value of 8 bit timer counter Hn and the set value of the CMPn0 register match the TOHn output level is inverted 8 bit timer counter Hn is cleared and the INTTMHn signal is out...

Page 326: ...H Count clock CMPn0 TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMPn1 FFH 00H 8 bit timer counter Hn count value Operation when CMPn0 register FFH CMPn1 register FEH Co...

Page 327: ...327 Figure 9 5 Operation Timing in PWM Output Mode 3 4 Operation when CMPn0 register 01H CMPn1 register 00H Count clock CMPn0 TMHEn INTTMHn TOHn TOLEVn 0 01H 00H 01H 00H 01H 00H 00H 01H 00H 01H CMPn1...

Page 328: ...nd the INTTMHn signal is generated 4 Even if the value of the CMPn1 register is changed that value is latched and not transferred to the register When the count value of 8 bit timer counter Hn and the...

Page 329: ...enable refer to CHAPTER 17 INTERRUPT EXCEPTION PROCESSING FUNCTION 1 Carrier generation In the carrier generator mode the CMPn0 register generates a waveform with the low level width of the carrier pu...

Page 330: ...M5n signal is synchronized with the count clock of 8 bit timer Hn and is output as the INTTM5Hn signal 2 The value of the NRZBn bit is transferred to the NRZn bit at the second clock from the rising e...

Page 331: ...r Hn is cleared and at the same time the register that is compared with 8 bit timer counter Hn changes from the CMPn0 register to the CMPn1 register 5 When the count value of 8 bit timer counter Hn an...

Page 332: ...peration was stopped TMHEn bit 0 be sure to set again even if setting the same value to the CMPn1 register 2 Set the values of the CMPn0 and CMPn1 registers in the range of 01H to FFH 3 In the carrier...

Page 333: ...register match the first INTTMHn signal is generated the carrier clock signal is inverted and the register that is compared with 8 bit timer counter Hn changes from the CMPn0 register to the CMPn1 reg...

Page 334: ...clock signal is inverted and the register that is compared with 8 bit timer counter Hn changes from the CMPn0 register to the CMPn1 register 8 bit timer counter Hn is cleared to 00H 4 When the count v...

Page 335: ...while the 8 bit timer Hn is operating The new value L to which the value of the register is to be changed is latched When the count value of the 8 bit timer counter Hn matches the value M of the CMPn1...

Page 336: ...ted at a specified interval Generation of count clock for watch timer When the main clock is used as the count clock for the watch timer a count clock fBRG is generated 10 1 2 Configuration The follow...

Page 337: ...selector selects the count clock fBGCS for interval timer BRG from fX fX 2 fX 4 and fX 8 4 8 bit counter The 8 bit counter counts the count clock fBGCS 5 Output control The output control controls sup...

Page 338: ...ation fX fX 2 fX 4 fX 8 5 MHz 200 ns 400 ns 800 ns 1 6 s 4 MHz 250 ns 500 ns 1 s 2 s BGCS1 0 0 1 1 BGCS0 0 1 0 1 Selection of input clock fBGCS Note After reset 00H R W Address FFFFF8B0H Clock for wat...

Page 339: ...egister This register can be read or written in 8 bit units Reset sets this register to 00H PRSCM7 PRSCM PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0 After reset 00H R W Address FFFFF8B1H Caution...

Page 340: ...unt clock supply for watch timer Set the count clock by using the PRSM BGCS1 and PRSM BGCS0 bits and the 8 bit compare value by using the PRSCM register so that the count clock frequency fBRG of the w...

Page 341: ...unctions can be used at the same time 10 2 2 Configuration The following shows the block diagram of the watch timer Figure 10 2 Block Diagram of Watch Timer Internal bus Watch timer operation mode reg...

Page 342: ...the INTWT signal generation time interval Selector that selects the generation time interval of the interval timer WT interrupt request signal INTWTI from 24 fW to 2 11 fW 4 8 bit counter The 8 bit co...

Page 343: ...WTM3 WTM2 WTM1 WTM0 WTM5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WTM4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 After reset 00H R W Address FFFFF680H 214 fW 0 5 s fW fXT 213 fW 0 25 s fW fXT 25 fW 977 s fW fXT 24 fW 48...

Page 344: ...ount value set in advance The interval time can be selected by the WTM WTM4 to WTM WTM7 bits Table 10 1 Interval Time of Interval Timer WTM7 WTM6 WTM5 WTM4 Interval Time 0 0 0 0 2 4 1 fW 488 s operati...

Page 345: ...s Interrupt time of watch timer 0 5 s Interval time T Interval time T nT nT 5 bit counter Count clock fW or fW 29 Watch timer interrupt INTWT Interval timer interrupt INTWTI Remarks 1 Assuming that th...

Page 346: ...lue stop operation When using the main clock as the count clock for interval timer WT the interval time of interval timer BRG can be set to any value but cannot be changed later it can be changed only...

Page 347: ...interrupt request signal INTWDT1 upon overflow of watchdog timer 1Note Generation of system reset signal WDTRES1 upon overflow of watchdog timer 1 Generation of maskable interrupt request signal INTW...

Page 348: ...4 fXW 213 INTWDT1 fXW Internal bus Watchdog timer mode register 1 WDTM1 Watchdog timer clock selection register WDCS Output controller Prescaler Clear Selector Remark INTWDTM1 Request signal for maska...

Page 349: ...his register sets the overflow time of watchdog timer 1 and the interval timer The WDCS register can be read or written in 8 bit or 1 bit units Reset sets this register to 00H 0 WDCS 0 0 0 0 WDCS2 WDC...

Page 350: ...ation clock RUN1 Stop counting Clear counter and start counting RUN1 0 1 Selection of operation mode of watchdog timer 1Note 1 WDTM1 0 0 WDTM14 WDTM13 0 0 0 After reset 00H R W Address FFFFF6C2H Inter...

Page 351: ...s generated The count operation of watchdog timer 1 stops in the STOP mode and IDLE mode Set the RUN1 bit to 1 before the STOP mode or IDLE mode is entered in order to clear watchdog timer 1 Because w...

Page 352: ...rval timer continues to operate in the HALT mode but it stops operating in the STOP mode and the IDLE mode Cautions 1 Once the WDTM14 bit is set to 1 thereby selecting the watchdog timer 1 mode the in...

Page 353: ...tion or clear once watchdog timer 2 and stop it within the next interval time Also write to the WDTM2 register for verification purposes only once even if the default settings reset mode interval time...

Page 354: ...ls refer to 3 4 8 1 b Access to special on chip peripheral I O register When the CPU operates on the subclock and the main clock oscillation is stopped When the CPU operates on the internal oscillatio...

Page 355: ...500 ms fXT 32 768 kHz 0 1 1 1 0 2 15 fXT 1000 ms fXT 32 768 kHz 0 1 1 1 1 2 16 fXT 2000 ms fXT 32 768 kHz 1 Operation stopped Note For frequency characteristics error of internal oscillation clock fR...

Page 356: ...ting ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again After the count operation starts write ACH to the WDTE register within the set program loop de...

Page 357: ...ble for controlling a stepping motor In the V850ES KE1 a 6 bit real time output port channel is provided The real time output port can be set in the port mode or real time output port mode in 1 bit un...

Page 358: ...her of these registers Moreover the data of both these registers can be read at once by specifying the address of either of these registers Table 12 2 shows the operation when the RTBL0 and RTBH0 regi...

Page 359: ...time output disabled Real time output enabled Control of real time output port m 0 to 5 RTPM0 0 RTPM05 RTPM04 RTPM03 RTPM02 RTPM01 RTPM00 After reset 00H R W Address FFFFF6E4H Cautions 1 To reflect r...

Page 360: ...XTR0Note 2 0 0 0 0 4 bits 1 channel 2 bits 1 channel 6 bits 1 channel BYTE0 0 1 Specification of channel configuration for real time output After reset 00H R W Address FFFFF6E5H Notes 1 The value of t...

Page 361: ...pecified as real time output disabled by the RTPM0 register output 0 If the real time output operation is disabled by clearing the RTPOE0 bit to 0 the RTPOUT00 to RTPOUT05 signals output 0 regardless...

Page 362: ...d RTBL0 registers is performed when the RTPOE0 bit 0 that value is transferred to real time output latches 0H and 0L respectively 2 Even if write is performed to the RTBH0 and RTBL0 registers when the...

Page 363: ...laced in high impedance by INTP0Note 1 pin are initialized Note 2 so settings for these ports must be performed again Notes 1 Regardless of the port settings P50 to P55 pins are all placed in high imp...

Page 364: ...H R W Address FFFFF806H Note For details on the SELPLL and PLLON bits refer to CHAPTER 5 CLOCK GENERATION FUNCTION Cautions 1 Before outputting a value to the real time output ports RTP00 to RTP05 sel...

Page 365: ...3 to 100 s 4 5 V AVREF0 5 5 V 4 8 to 100 s 4 0 V AVREF0 4 5 V 6 to 100 s 2 85 V AVREF0 4 0 V 14 to 100 s 2 7 V AVREF0 2 85 V Power fail detection function Caution When using the A D converter operate...

Page 366: ...parator Controller Edge detector ADTRG INTTM010 ADCR ADCRH register PFT register ADS register ADM register PFEN PFCM PFM register Internal bus SAR register Comparator Tap selector Selector Selector Ta...

Page 367: ...gnificant bit MSB When the least significant bit LSB has been converted to a digital value end of A D conversion the contents of the SAR register are transferred to the ADCR register The SAR register...

Page 368: ...arison threshold register PFT This register sets the threshold to be compared with the ADCR register 13 4 Registers The A D converter is controlled by the following registers A D converter mode regist...

Page 369: ...ontrolled by the ADCS bit and it takes 1 s high speed mode or 14 s normal mode after operation is started until it is stabilized Therefore the ADCS2 bit is set to 1 A D conversion is started at least...

Page 370: ...72 fXX Setting prohibited Setting prohibited 9 0 Setting prohibited 0 1 0 1 0 48 fXX Setting prohibited Setting prohibited 6 0 Setting prohibited 0 1 0 1 1 24 fXX Setting prohibited Setting prohibite...

Page 371: ...voltage generator automatically turns off In the software trigger mode ADS TRG bit 0 use of the first A D conversion result is prohibited In the hardware trigger mode TRG bit 1 use the A D conversion...

Page 372: ...de Hardware trigger mode Trigger mode selection ADTMDNote 2 0 1 External trigger ADTRG pin input Timer trigger INTTM010 signal generated Specification of hardware trigger mode Notes 1 The EGA1 and EGA...

Page 373: ...read in the lower 6 bits In the ADCRH register the higher 8 bits of the conversion results are read Reset makes these registers undefined After reset Undefined R Address FFFFF204H ADCR AD9 AD8 AD7 AD6...

Page 374: ...t voltage AVREF0 Voltage of AVREF0 pin ADCR Value in the ADCR register Note The lower 6 bits of the ADCR register are fixed to 0 The following shows the relationship between the analog input voltage a...

Page 375: ...able PFM PFCM 0 0 0 0 0 0 PFCM 0 1 Interrupt request signal INTAD generated when ADCR PFT Interrupt request signal INTAD generated when ADCR PFT Selection of power fail comparison mode After reset 00H...

Page 376: ...Reset sets this register to 00H PFT After reset 00H R W Address FFFFF203H 7 6 5 4 3 2 1 0 Cautions 1 Writing the PFT register is prohibited during A D conversion operation ADM ADCS bit 1 in the normal...

Page 377: ...r than 1 2 AVREF0 the MSB of the SAR register remains set to 1 If the analog input voltage is less than 1 2 AVREF0 the MSB is cleared to 0 8 Next bit 8 of the SAR register is automatically set to 1 an...

Page 378: ...e signal input to the ADTRG pin is specified by using the ADS EGA1 and ADS EGA0 bits When the specified valid edge is detected A D conversion is started When A D conversion is completed the A D conver...

Page 379: ...e high speed mode ADM ADHS1 ADM ADHS0 bits 01 or 10 A D conversion is aborted In the software trigger mode A D conversion is started from the beginning again In the hardware trigger mode the A D conve...

Page 380: ...ts for a trigger after it has completed A D conversion of the analog signals specified by the ADS register and input from the ANI0 pin If anything is written to the ADM ADS PFM and PFT registers durin...

Page 381: ...ample A D conversion Data 1 ANI0 Data 2 ANI1 Data 3 ANI2 Data 4 ANI3 Data 1 ANI0 Data 2 ANI1 Data 3 ANI2 Data 4 ANI3 ADCR INTAD Conversion start Set ADCS bit 1 Conversion end ANI3 ANI0 ANI1 ANI2 Data...

Page 382: ...FCM bits 1 the conversion result and the value of the PFT register are compared when conversion ends and the INTAD signal is generated only if ADCRH PFT Because when the PFEN bit 1 the conversion resu...

Page 383: ...erated Changing the channel 6 Change the channel by setting the ADS2 to ADS0 bits 7 Transfer the A D conversion data to the ADCR register 8 The INTAD signal is generated Ending A D conversion 9 Clear...

Page 384: ...sfer the A D conversion data to the ADCR register 8 Compare the ADCRH register with the PFT register An interrupt request signal INTAD is generated when the conditions match Changing the channel 9 Cha...

Page 385: ...7 pin input voltages within the specified range If a voltage of AVREF0 or higher or AVSS or lower even if within the absolute maximum ratings is input to these pins the conversion value of the channel...

Page 386: ...nction alternately as input port pins P70 to P77 When performing A D conversion by selecting any of the ANI0 to ANI7 pins do not execute an input instruction to port 7 during conversion This may decre...

Page 387: ...0 to 7 m 0 to 7 8 Conversion results immediately after A D conversion start If the ADM ADCS bit is set to 1 within 1 s high speed mode or 14 s normal mode after the ADM ADCS2 bit has been set to 1 or...

Page 388: ...tarted after A D converter operation is enabled When using a set in which the A D conversion time must be strictly observed care is required for the contents shown in Figure 13 10 and Table 13 4 Figur...

Page 389: ...7 fXX 8 fXX 0 1 0 0 1 72 fXX 36 fXX 10 fXX 11 fXX 6 fXX 7 fXX 0 1 0 1 0 48 fXX 24 fXX 9 fXX 10 fXX 5 fXX 6 fXX 0 1 0 1 1 24 fXX 12 fXX 8 fXX 9 fXX 4 fXX 5 fXX 0 1 1 0 0 224 fXX 176 fXX 11 fXX 12 fXX 7...

Page 390: ...ult the following phenomena may occur When the same channel is used for A D conversions if the voltage is higher or lower than the previous A D conversion then hysteresis characteristics may appear wh...

Page 391: ...following formula regardless of the resolution 1 FSR Max value of analog input voltage that can be converted Min value of analog input voltage that can be converted 100 AVREF0 0 100 AVREF0 100 1 LSB...

Page 392: ...or zero scale error full scale error integral linearity error and differential linearity error in the characteristics table Figure 13 13 Quantization Error 0 0 1 1 Digital output Quantization error 1...

Page 393: ...11 6 Differential linearity error While the ideal width of code output is 1 LSB this indicates the difference between the actual measurement value and the ideal value This indicates the basic characte...

Page 394: ...ale error are 0 Figure 13 17 Integral Linearity Error 0 AVREF0 Digital output Analog input Integral linearity error Ideal line 1 1 0 0 8 Conversion time This expresses the time from when the analog in...

Page 395: ...equest signal INTSRn Interrupt is generated when receive data is transferred from the receive shift register to the RXBn register after serial transfer is completed during a reception enabled state Tr...

Page 396: ...0 when the ASISn register is read 3 Asynchronous serial interface transmit status register n ASIFn The ASIFn register is an 8 bit register that indicates the status when a transmit operation is perfo...

Page 397: ...sion completion interrupt request signal INTSTn is generated synchronized with the completion of transmission of one frame This register cannot be directly manipulated 9 Transmit buffer register n TXB...

Page 398: ...10H UARTEn Control of operating clock 0 Stop clock supply to UARTn 1 Supply clock to UARTn If the UARTEn bit is cleared to 0 UARTn is asynchronously reset Note If the UARTEn bit 0 UARTn is reset To op...

Page 399: ...bits SLn Specification of stop bit length of transmit data 0 1 bit 1 2 bits To overwrite the SLn bit first clear 0 the TXEn bit Since reception is always done with a stop bit length of 1 the SLn bit...

Page 400: ...n clock oscillation is stopped When the CPU operates on the internal oscillation clock 7 0 ASISn n 0 1 6 0 5 0 4 0 3 0 2 PEn 1 FEn 0 OVEn After reset 00H R Address ASIS0 FFFFFA03H ASIS1 FFFFFA13H PEn...

Page 401: ...hen the ASIMn UARTEn or ASIMn TXEn bit is cleared to 0 or when data has been transferred to the transmission shift register 1 Data to be transferred next exists in TXBn register Data exists in TXBn re...

Page 402: ...t refer to 14 5 4 Receive operation If reception is disabled ASIMn RXEn bit 0 the contents of the RXBn register are retained and no processing is performed for transferring data to the RXBn register e...

Page 403: ...ta is transferred to the transmit shift register and a transmission completion interrupt request signal INTSTn is generated synchronized with the completion of the transmission of one frame from the t...

Page 404: ...0 UARTE0 bit 1 and ASIM0 TXE0 bit 1 or ASIM0 UARTE0 bit 1 and ASIM0 RXE0 bit 1 However do not set the SBRT0 bit 1 or SBTT0 bit 1 by writing the same value during SBF reception SBRF0 bit 1 or SBF trans...

Page 405: ...the mode returns to the SBF reception mode The status of the SBRF0 bit is held 1 2 Before setting the SBRT0 bit make sure that the UARTE0 and RXE0 bits 1 After setting the SBRT0 bit to 1 do not clear...

Page 406: ...er If SELCNT0 ISEL00 is set to 1 RXD0 pin is selected when LIN is used the transfer rate for calculating the baud rate error can be checked using TM01 This register can be read or written in 8 bit or...

Page 407: ...Reception error interrupt request signal INTSREn When reception is enabled the INTSREn signal is generated according to the logical OR of the three types of reception errors explained for the ASISn r...

Page 408: ...arity bit and stop bits as shown in Figure 14 2 The character bit length within one data frame the type of parity and the stop bit length are specified according to the ASIMn register Also data is tra...

Page 409: ...Bn register When a transmit operation is started the data in the TXBn register is transferred to the transmit shift register Then the transmit shift register outputs data to the TXDn pin the transmit...

Page 410: ...ser s Manual U16896EJ2V0UD 410 Figure 14 3 UARTn Transmission Completion Interrupt Timing Start Stop D0 D1 D2 D6 D7 Parity Parity TXDn output INTSTn output Start D0 D1 D2 D6 D7 TXDn output INTSTn outp...

Page 411: ...d only the TXBFn bit during continuous transmission TXBFn Whether or Not Writing to TXBn Register Is Enabled 0 Writing is enabled 1 Writing is not enabled Caution When transmission is performed contin...

Page 412: ...currence Wait for interrupt Required number of transfers performed Write transmit data to TXBn register Write second byte transmit data to TXBn register Write transmit data to TXBn register When readi...

Page 413: ...rt bit 10 Note Refer to 14 7 Cautions 2 ASIFn Register Transmission Starting Procedure Internal Operation TXBFn TXSFn Set transmission mode 1 Start transmission unit 0 0 Write data 1 1 0 2 Generate st...

Page 414: ...p bit Stop bit ASIFn Register Transmission End Procedure Internal Operation TXBFn TXSFn 6 Transmission of data m 2 is in progress 1 1 7 INTSTn interrupt occurs Read ASIFn register confirm that TXBFn b...

Page 415: ...ve operation A receive operation is started by the detection of a start bit The RXDn pin is sampled using the serial clock from baud rate generator n BRGn 3 Reception completion interrupt When the RXE...

Page 416: ...nput INTSRn output RXBn register Parity Stop Cautions 1 Be sure to read the RXBn register even when a reception error occurs If the RXBn register is not read an overrun error will occur at the next da...

Page 417: ...e parity of the reception data FEn Framing error No stop bit was detected OVEn Overrun error The reception of the next data was completed before data was read from the RXBn register 1 Separation of re...

Page 418: ...number is odd 2 Odd parity i During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit i...

Page 419: ...is not delivered to the internal circuit refer to Figure 14 11 Refer to 14 6 1 1 Base clock regarding the base clock Also since the circuit is configured as shown in Figure 14 10 internal processing d...

Page 420: ...t and corrects the baud rate error Therefore communication is possible when the baud rate error in the slave is 15 or less 1 SBF transmission reception format Figures 14 12 and 14 13 outline the trans...

Page 421: ...upt signal is output and the mode returns to the SBF reception mode 3 If SBF reception ends normally an interrupt request signal is output The timer is enabled by an SBF reception completion interrupt...

Page 422: ...n enabled status is entered and SBF transmission is started by setting the ASICL0 SBTT0 bit to 1 Thereafter a low level of bits 13 to 20 set by ASICL0 SBL02 to ASICL0 SBL00 bits is output Following th...

Page 423: ...completion interrupt request signal INTSR0 is output The ASICL0 SBRF0 bit is automatically cleared and SBF reception ends Error detection for the ASIS0 PE0 ASIS0 FE0 and ASIS0 OVE0 bits is suppressed...

Page 424: ...Rate Generator n BRGn fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 fXX 1 024 External input ASCK0Note 2 fUCLK Note 1 Selector UARTEn 8 bit counter Match detector Baud rate BRGCn MDLn...

Page 425: ...le This register can be read or written in 8 bit units Reset sets this register to 00H Caution Clear the ASIMn UARTEn bit to 0 before rewriting the TPSn3 to TPSn0 bits 7 0 CKSRn n 0 1 6 0 5 0 4 0 3 TP...

Page 426: ...MDLn3 2 MDLn2 1 MDLn1 0 MDLn0 After reset FFH R W Address BRGC0 FFFFFA07H BRGC1 FFFFFA17H MDLn7 MDLn6 MDLn5 MDLn4 MDLn3 MDLn2 MDLn1 MDLn0 Set value k Serial clock 0 0 0 0 0 Setting prohibited 0 0 0 0...

Page 427: ...1 Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination 2 Make sure that the baud rate error during reception is within the allowable...

Page 428: ...41H 65 0 16 24000 fXX 32 0DH 13 0 16 fXX 2 A7H 167 0 20 fXX 16 0DH 13 0 16 31250 fXX 32 0AH 10 0 00 fXX 32 08H 8 0 00 fXX 16 0AH 10 0 33600 fXX 2 95H 149 0 13 fXX 2 77H 119 0 04 fXX 95H 149 0 13 3840...

Page 429: ...t 7 Parity bit Minimum allowable transfer rate Maximum allowable transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figu...

Page 430: ...e baud rate error of UARTn and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values Table 14 5 Maximum and Mi...

Page 431: ...h 1 Transfer rate 11 FL 2 fUCLK 14 7 Cautions Cautions to be observed when using UARTn are shown below 1 When the supply of clocks to UARTn is stopped for example in IDLE or STOP mode operation stops...

Page 432: ...clock signals can be selected 7 master clocks and 1 slave clock 3 wire type SO0n Serial transmit data output SI0n Serial receive data input SCK0n Serial clock I O Interrupt sources 1 type Transmissio...

Page 433: ...ion operations are started up by accessing the buffer register 5 Clocked serial interface receive buffer register n SIRBn The SIRBn register is a 16 bit buffer register that stores receive data 6 Cloc...

Page 434: ...ector The selector selects the serial clock to be used 14 Serial clock controller Controls the serial clock supply to the shift register Also controls the clock output to the SCK0n pin when the intern...

Page 435: ...uffer register SOTBn SOTBnL Receive buffer register SIRBn SIRBnL Shift register SIO0n SIO0nL Initial transmit buffer register SOTBFn SOTBFnL Interrupt controller Clock start stop control clock phase c...

Page 436: ...0n register controls the CSI0n operation This register can be read or written in 8 bit or 1 bit units however CSOTn bit is read only Reset sets this register to 00H Caution Overwriting the TRMDn CCLn...

Page 437: ...transmission reception is started by writing data to the SOTBn register CCLn Specification of data length 0 8 bits 1 16 bits DIRn Specification of transfer direction mode MSB LSB 0 First bit of trans...

Page 438: ...SO0n output SCK0n I O SI0n input DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 1 Type 2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO0n output SCK0n I O SI0n input 1 0 Type 3 DO7 DO6 DO5 DO4 DO3...

Page 439: ...e SIRBn register only when a 16 bit data length has been set CSIM0n CCLn bit 1 Read the SIRBnL register only when an 8 bit data length has been set CCLn bit 0 2 When the single transfer mode has been...

Page 440: ...reset input this register is also cleared to 0000H by clearing 0 the CSIM0n CSI0En bit Cautions 1 The receive operation is not started even if data is read from the SIRBEn and SIRBEnL registers 2 The...

Page 441: ...ster only when a 16 bit data length has been set CSIM0n CCLn bit 1 Access the SOTBnL register only when an 8 bit data length has been set CCLn bit 0 2 When the single transfer mode is set CSIM0n AUTOn...

Page 442: ...he SOTBFn register and SOTBFnL register only when a 16 bit data length has been set CSIM0n CCLn bit 1 and only when an 8 bit data length has been set CCLn bit 0 respectively and only in the idle state...

Page 443: ...CSI0En bit Caution Read the SIO0n register and SIO0nL register only when a 16 bit data length has been set CSIM0n CCLn bit 1 and only when an 8 bit data length has been set CCLn bit 0 respectively an...

Page 444: ...next to this register to start the next transmission reception Storing the data to be transmitted firstNote 2 Before starting transmission reception writing to SOTBn write the data to be transmitted f...

Page 445: ...al INTCSI0n The INTCSI0n signal is set 1 upon completion of data transmission reception Writing to the CSIM0n register clears 0 the INTCSI0n signal Caution The delay mode CSIM0n CSITn bit 1 is valid o...

Page 446: ...O2 DO1 DO0 Input clock SCK0n I O SI0n input SO0n output Reg_R W INTCSI0n signal CSOTn bit Delay b Transmit receive type 4 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SC...

Page 447: ...ing to the SOTBn SOTBnL register In the slave mode the operation must be enabled beforehand CSIM0n CSI0En bit 1 When communication is started the value of the CSIM0n CSOTn bit becomes 1 transmission e...

Page 448: ...eive type 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 55H AAH AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCK0n I O SO0n output SI0n input Reg_R W SOTBnL register SIO0nL register SIRBnL register CSOTn bit INTCSI0n sign...

Page 449: ...eive type 2 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCK0n I O SO0n output SI0n input Reg_R W SOTBnL register SIO0nL register SIRBnL register CSOTn bit INTCSI0n signal 55H A...

Page 450: ...SIRBnL registerNote reserve next transfer 4 Repeat step 3 N 2 times N Number of transfer data Ignore the interrupt triggered by reception of the N 1 th data at this time the SIRBEnL register can be re...

Page 451: ...Remarks 1 Reg_RD Internal signal This signal indicates that the SIRBnL register has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal 2 n...

Page 452: ...BnL register start transfer 4 When the transmission reception completion interrupt request signal INTCSI0n has been generated write the next data to the SOTBnL register reserve next transfer Read the...

Page 453: ...din 5 din 2 din 3 din 4 din 5 Remarks 1 Reg_WR Internal signal This signal indicates that the SOTBnL register has been written Reg_RD Internal signal This signal indicates that the SIRBnL register ha...

Page 454: ...er must be prepared with the period shown in Figure 15 6 Figure 15 6 Timing Chart of Next Transfer Reservation Period 1 2 a When data length 8 bits transmit receive type 1 SCK0n I O INTCSI0n signal Re...

Page 455: ...ming Chart of Next Transfer Reservation Period 2 2 c When data length 8 bits transmit receive type 2 SCK0n I O INTCSI0n signal Reservation period 6 5 SCK0n cycles d When data length 16 bits transmit r...

Page 456: ...i In case of conflict between transfer request clear and register access Since transfer request clear has higher priority the next transfer request is ignored Therefore transfer is interrupted and nor...

Page 457: ...t phase error transfer error results refer to Figure 15 8 In the transmission reception mode the value of the SOTBFn register is retransmitted and illegal data is sent Figure 15 8 Interrupt Request an...

Page 458: ...put 0 Don t care Don t care Don t care Fixed to high level 1 1 1 High impedance 1 Other than above Fixed to low level Remark n 0 1 2 SO0n pin When the CSI0n operation is disabled CSI0En bit 0 the SO0n...

Page 459: ...refore be used to reduce power consumption 2 I2 C bus mode multimaster supported This mode is used for 8 bit data transfers with several devices via two lines a serial clock SCL0 line and a serial dat...

Page 460: ...C0 CL01 CL00 CLX0 IIC clock select register 0 IICCL0 STCF0 IICBSY0 STCEN0IICRSV0 IIC flag register 0 IICF0 IIC function expansion register 0 IICX0 fXX Clear Slave address register 0 SVA0 Match signal...

Page 461: ...ample is shown below Figure 16 2 Serial Bus Configuration Example Using I2 C Bus SDA SCL SDA VDD VDD SCL SDA SCL Slave CPU3 Address 3 SDA SCL Slave IC Address 4 SDA SCL Slave IC Address N Master CPU1...

Page 462: ...s register 0 SVA0 The SVA0 register sets local addresses when in slave mode The SVA0 register can be read or written in 8 bit units Reset sets this register to 00H 3 SO latch The SO latch is used to r...

Page 463: ...o the falling edge of the serial clock 12 Start condition generator This circuit generates a start condition when the IICC0 STT0 bit is set However in the communication reservation disabled status IIC...

Page 464: ...register 0 SVA0 Remark For the alternate function pin settings refer to Table 4 12 Settings When Port Pins Are Used for Alternate Functions 1 IIC control register 0 IICC0 The IICC0 register is used t...

Page 465: ...red to 0 The standby mode following exit from communications remains in effect until the following communications entry conditions are met After a stop condition is detected restart is in master mode...

Page 466: ...e ninth clock during address transfer independently of the setting of this bit The setting of this bit is valid when the address transfer is completed When in master mode a wait is inserted at the fal...

Page 467: ...nerated In the wait state when master device Generates a restart condition after releasing the wait Cautions concerning set timing For master reception Cannot be set to 1 during transfer Can be set to...

Page 468: ...ng the wait period that follows output of eight clocks note that a stop condition will be generated during the high level period of the ninth clock The WTIM0 bit should be changed from 0 to 1 during t...

Page 469: ...tus 0 Slave device status or communication standby status 1 Master device communication status Condition for clearing MSTS0 bit 0 Condition for setting MSTS0 bit 1 When a stop condition is detected Wh...

Page 470: ...of the eighth clock TRC0 Detection of transmit receive status 0 Receive status other than transmit status The SDA0 line is set for high impedance 1 Transmit status The value in the SO latch is enabled...

Page 471: ...ansfer period is in effect Condition for clearing STD0 bit 0 Condition for setting STD0 bit 1 When a stop condition is detected At the rising edge of the next byte s first clock following address tran...

Page 472: ...STCF0 and IICBSY0 bits are read only The IICRSV0 bit can be used to enable disable the communication reservation function refer to 16 13 Communication Reservation The STCEN0 bit can be used to set th...

Page 473: ...tus flag Condition for clearing STCEN0 bit 0 Detection of start condition Reset Condition for setting STCEN0 bit 1 Setting by instruction STCEN0 0 1 After operation is enabled IICE0 bit 1 enable gener...

Page 474: ...n for clearing CLD0 bit 0 Condition for setting CLD0 bit 1 When the SCL0 pin is at low level When the IICE0 bit changes from 1 to 0 operation stop Reset When the SCL0 pin is at high level DAD0 Detecti...

Page 475: ...ss FFFFFD85H 7 6 5 4 3 2 1 0 IICX0 0 0 0 0 0 0 0 CLX0 6 I2 C0 transfer clock setting method The I2 C0 transfer clock frequency fSCL is calculated using the following expression fSCL 1 m T tR tF m 12 2...

Page 476: ...tion shift operations that is synchronized with the serial clock The IIC0 register can be read or written in 8 bit units but data should not be written to the IIC0 register during a data transfer Acce...

Page 477: ...Input is Schmitt input SDA0 This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input Since outputs from the ser...

Page 478: ...rated by either the master or slave device normally it is generated by the device that receives 8 bit data The serial clock SCL0 is continuously output by the master device However in the slave device...

Page 479: ...ddress or extension code is received during slave device operation The slave address and the eighth bit which specifies the transfer direction as described in 16 5 3 Transfer direction specification b...

Page 480: ...ation is enabled Transmission of the eighth bit following the 7 address data bits causes the IICS0 TRC0 bit to be set Normally set the ACKE0 bit to 1 for reception TRC0 bit 0 When the slave device is...

Page 481: ...ed when serial transfer from the master device to the slave device has been completed Stop conditions can be detected when the device is used as a slave Figure 16 9 Stop Condition H SCL0 SDA0 A stop c...

Page 482: ...next data transfer can begin Figure 16 10 Wait State 1 2 a When master device has a nine clock wait and slave device has an eight clock wait master transmission slave reception and IICC0 ACKE0 bit 1...

Page 483: ...d according to previously set ACKE0 bit value Transfer lines Wait state from master and slave Wait state from slave A wait state is automatically generated after a start condition is generated Moreove...

Page 484: ...state or to complete data transmission set the WREL0 bit to 1 To generate a restart condition after canceling wait state set the STT0 bit to 1 To generate a stop condition after canceling wait state...

Page 485: ...ls INTIIC0 The following shows the value of the IICS0 register at the INTIIC0 interrupt request signal generation timing and at the INTIIC0 signal timing Remark ST Start condition AD6 to AD0 Address R...

Page 486: ...Note S4 IICS0 register 1000XX00B 5 IICS0 register 00000001B Note To generate a stop condition set the WTIM0 bit to 1 and change the timing of the generation of the interrupt request signal INTIIC0 Rem...

Page 487: ...start condition set the WTIM0 bit to 1 and change the timing of the generation of the interrupt request signal INTIIC0 2 Clear the WTIM0 bit to 0 to make the settings original 3 To generate a stop co...

Page 488: ...r 1010XX00B 5 IICS0 register 00000001B Note To generate a stop condition set the WTIM0 bit to 1 and change the timing of the generation of the interrupt request signal INTIIC0 Remark S Always generate...

Page 489: ...1 IICS0 register 0001X110B S2 IICS0 register 0001X000B S3 IICS0 register 0001X000B 4 IICS0 register 00000001B Remark S Always generated Generated only when IICC0 SPIE0 bit 1 X don t care 2 When WTIM0...

Page 490: ...CS0 register 0001X110B S4 IICS0 register 0001X000B 5 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t care 2 When WTIM0 bit 1 after restart address match ST A...

Page 491: ...X010B S4 IICS0 register 0010X000B 5 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t care 2 When WTIM0 bit 1 after restart address mismatch extension code ST...

Page 492: ...CS0 register 0001X000B S3 IICS0 register 00000110B 4 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t care 2 When WTIM0 bit 1 after restart address mismatch n...

Page 493: ...3 4 S1 IICS0 register 0010X010B S2 IICS0 register 0010X000B S3 IICS0 register 0010X000B 4 IICS0 register 00000001B Remark S Always generated Generated only when IICC0 SPIE0 bit 1 X don t care 2 When W...

Page 494: ...X110B S4 IICS0 register 0001X000B 5 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t care 2 When WTIM0 bit 1 after restart address match ST AD6 to AD0 R W ACK...

Page 495: ...gister 0010X000B 5 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t care 2 When WTIM0 bit 1 after restart extension code reception ST AD6 to AD0 R W ACK D7 to...

Page 496: ...X000B S3 IICS0 register 00000110B 4 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t care 2 When WTIM0 bit 1 after restart address mismatch not extension code...

Page 497: ...esult by each INTIIC0 interrupt occurrence 1 When arbitration loss occurs during transmission of slave address data 1 When IICC0 WTIM0 bit 0 ST AD6 to AD0 R W ACK D7 to D0 ACK D7 to D0 ACK SP S1 S2 S3...

Page 498: ...register 0010X000B S3 IICS0 register 0010X000B 4 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t care 2 When WTIM0 bit 1 ST AD6 to AD0 R W ACK D7 to D0 ACK...

Page 499: ...ration loss occurs during transmission of slave address data ST AD6 to AD0 R W ACK D7 to D0 ACK D7 to D0 ACK SP S1 2 S1 IICS0 register 01000110B 2 IICS0 register 00000001B Remark S Always generated Ge...

Page 500: ...ACK SP S1 S2 3 S1 IICS0 register 10001110B S2 IICS0 register 01000000B 3 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 2 When WTIM0 bit 1 ST AD6 to AD0 R W ACK D7...

Page 501: ...1000X110B S2 IICS0 register 01000110B 3 IICS0 register 00000001B Remarks 1 S Always generated Generated only when SPIE0 bit 1 X don t care 2 Dn D6 to D0 2 Extension code ST AD6 to AD0 R W ACK D7 to D...

Page 502: ...502 5 When loss occurs due to stop condition during data transfer ST AD6 to AD0 R W ACK D7 to Dn SP S1 2 S1 IICS0 register 1000X110B 2 IICS0 register 01000001B Remarks 1 S Always generated Generated...

Page 503: ...2 IICS0 register 1000X000B WTIM0 bit 1 S3 IICS0 register 1000X100B WTIM0 bit 0 S4 IICS0 register 01000000B 5 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t...

Page 504: ...S3 4 S1 IICS0 register 1000X110B S2 IICS0 register 1000X000B WTIM0 bit 1 S3 IICS0 register 1000XX00B 4 IICS0 register 01000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t care...

Page 505: ...IICS0 register 1000X000B WTIM0 bit 1 S3 IICS0 register 1000X100B WTIM0 bit 0 S4 IICS0 register 01000100B 5 IICS0 register 00000001B Remark S Always generated Generated only when SPIE0 bit 1 X don t ca...

Page 506: ...l occurs at the falling edge of the eighth clock When the address does not match after restart the INTIIC0 signal is generated at the falling edge of the ninth clock but no wait occurs 2 If the receiv...

Page 507: ...n in I2 C bus mode the master device can select a particular slave device by transmitting the corresponding slave address Address match detection is performed automatically by hardware An INTIIC0 inte...

Page 508: ...Higher 4 bits of data match IICS0 EXC0 bit 1 7 bits of data match IICS0 COI0 bit 1 3 Since the processing after the INTIIC0 signal occurs differs according to the data that follows the extension code...

Page 509: ...ration loss flag IICS0 ALD0 bit is set 1 via the timing by which the arbitration loss occurred and the SCL0 and SDA0 lines are both set for high impedance which releases the bus The arbitration loss i...

Page 510: ...ion When the SCL0 pin is at low level while attempting to generate a restart condition At falling edge of eighth or ninth clock following byte transfer Note 1 Notes 1 When the IICC0 WTIM0 bit 1 an INT...

Page 511: ...ease due to an interrupt request INTIIC0 occurrence detecting a stop condition and then writing the address to the IIC0 register Before detecting a stop condition data written to the IIC0 register is...

Page 512: ...STD0 Generated by master with bus access IIC0 IIC shift register 0 STT0 Bit 1 of IIC control register 0 IICC0 STD0 Bit 1 of IIC status register 0 IICS0 SPD0 Bit 0 of IIC status register 0 IICS0 Commun...

Page 513: ...TS0 0 Communication reservation Note Generate start condition Sets STT0 flag communication reservation Gets wait period set by software refer to Table 16 6 Confirmation of communication reservation Cl...

Page 514: ...itration results in neither master nor slave operation When an extension code is received and slave operation is disabled ACK is not returned and the bus was released when the IICC0 LREL0 bit was set...

Page 515: ...is set to 1 while communications with other devices are in progress the start condition may be detected depending on the status of the communication line Be sure to set the IICC0 IICE0 bit to 1 when...

Page 516: ...sed state This flowchart is broadly divided into the initial settings communication waiting and communication processing The processing when the V850ES KE1 loses in arbitration and is specified as the...

Page 517: ...tart condition generation Communication start address transfer direction specification Waiting for ACK detection Waiting for data transmission Transmission start Communication processing Initial setti...

Page 518: ...ection Local address setting Start condition setting communication start request issued no communication start request Waiting for slave specification from another master Waiting for communication sta...

Page 519: ...op condition detection and start condition generation by communication reservation function No INTIIC0 interrupt occurred Yes Yes No No A C STT0 1 Wait Slave operation Yes IICBSY0 0 EXC0 1 or COI0 1 C...

Page 520: ...o Yes ACKD0 1 No Yes No C 2 Yes MSTS0 1 No Yes Transfer completed No Yes ACKD0 1 No 2 Yes MSTS0 1 No 2 Waiting for ACK detection Yes No INTIIC0 interrupt occurred Yes MSTS0 1 No C 2 Yes EXC0 1 or COI0...

Page 521: ...nication not in progress Communication mode Data communication in progress valid address detection stop condition detection ACK from master not detected address mismatch 2 Ready flag This flag indicat...

Page 522: ...on flag 1 Read IIC0 Clear ready flag Clear ready flag Communication direction flag 1 WREL0 1 ACKD0 1 Clear communication mode flag WREL0 1 Write IIC0 IICC0 XXH ACKE0 WTIM0 1 SPIE0 0 IICE0 1 SVA0 XXH L...

Page 523: ...address matches the communication mode is set and wait is released and operation returns from the interrupt the ready flag is cleared 3 For data transmission reception when the ready flag is set oper...

Page 524: ...master device transmits the IICS0 TRC0 bit that specifies the data transfer direction and then starts serial communication with the slave device The IIC0 register s shift operation is synchronized wit...

Page 525: ...L L L L H H H L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slave...

Page 526: ...L H H H H L L L L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slav...

Page 527: ...MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slave device 1 2 3 4 5 6 7 8...

Page 528: ...0 SPD0 WTIM0 H H L L L H L ACKE0 MSTS0 STT0 L L SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Process...

Page 529: ...L L L L L L H H L L L L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing b...

Page 530: ...WTIM0 H H L L L ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIIC0 TRC0 SCL0 SDA0 Processing by master device Transfer lines Processing by slave d...

Page 531: ...tarted by the TRAP instruction software exception or by generation of an exception event fetching of an illegal opcode exception trap 17 1 1 Features Interrupt Source V850ES KE1 External 1 channel NMI...

Page 532: ...in valid edge input Pin 00B0H 000000B0H nextPC PIC2 4 INTP3 INTP3 pin valid edge input Pin 00C0H 000000C0H nextPC PIC3 5 INTP4 INTP4 pin valid edge input Pin 00D0H 000000D0H nextPC PIC4 6 INTP5 INTP5...

Page 533: ...TMP 03B0H 000003B0H nextPC TP0CCIC0 Maskable Interrupt 49 INTTP0CC1 TMP0 capture 1 compare 1 match TMP 03C0H 000003C0H nextPC TP0CCIC1 Note Only in the PD703302Y 70F3302Y Remarks 1 Default priority T...

Page 534: ...d in a sequence determined by the following priority order the interrupt request signals with low priority level are ignored INTWDT2 INTWDT1 NMI If during NMI processing an NMI INTWDT1 or INTWDT2 requ...

Page 535: ...essing NMI and INTWDT2 requests simultaneously generated Main routine System reset NMI INTWDT1 request simultaneously generated INTWDT1 processing NMI and INTWDT1 requests simultaneously generated Mai...

Page 536: ...Hold pending Main routine System reset NMI request NMI request NMI processing INTWDT1 processing INTWDT1 request NP 0 NP 0 Main routine System reset INTWDT2 request NMI processing INTWDT2 processing...

Page 537: ...higher halfword FECC of ECR 4 Sets the PSW NP and PSW ID bits to 1 and clears the PSW EP bit to 0 5 Loads the handler address 00000010H 00000020H 00000030H of the non maskable interrupt to the PC and...

Page 538: ...s of the restored PC and PSW Figure 17 3 shows the processing flow of the RETI instruction Figure 17 3 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing...

Page 539: ...on maskable interrupt servicing is in progress This flag is set when a non maskable interrupt request has been acknowledged and masks all non maskable requests to prevent multiple interrupts 0 NP EP I...

Page 540: ...e same priority level cannot be nested To use multiple interrupts it is necessary to save EIPC and EIPSW to memory or a register before executing the EI instruction and restore EIPC and EIPSW to the o...

Page 541: ...essing Interrupt mask released Priority higher than that of interrupt currently being serviced Interrupt request pending PSW NP PSW ID Interrupt request pending No No No No 1 0 1 0 INT input Yes Yes Y...

Page 542: ...W Figure 17 5 shows the processing flow of the RETI instruction Figure 17 5 RETI Instruction Processing RETI instruction Original processing restored PC PSW ISPR corresponding bitNote EIPC EIPSW 0 PSW...

Page 543: ...e generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request default priority level beforehand For more information refer to Table...

Page 544: ...ing even if interrupts are enabled because its priority is the same as that of g Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e Interru...

Page 545: ...cing of p Servicing of q Servicing of r EI If levels 3 to 0 are acknowledged Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged beca...

Page 546: ...rrupt request b level 1 Note 1 Interrupt request c level 1 Note 2 Servicing of interrupt request b Servicing of interrupt request c Servicing of interrupt request a Interrupt requests b and c are ackn...

Page 547: ...ed Interrupt request generated xxIFn 0 1 Interrupt request flagNote xxICn xxMKn 0 0 0 xxPRn2 xxPRn1 xxPRn0 Enables interrupt servicing Disables interrupt servicing pending xxMKn 0 1 Interrupt mask fla...

Page 548: ...CSI0PR10 FFFFF130H SREIC0 SREIF0 SREMK0 0 0 0 SREPR02 SREPR01 SREPR00 FFFFF132H SRIC0 SRIF0 SRMK0 0 0 0 SRPR02 SRPR01 SRPR00 FFFFF134H STIC0 STIF0 STMK0 0 0 0 STPR02 STPR01 STPR00 FFFFF136H SREIC1 SR...

Page 549: ...K0 1 WDT1MK After reset FFFFH R W Address IMR0 FFFFF100H IMR0L FFFFF100H IMR0H FFFFF101H After reset FFFFH R W Address IMR1 FFFFF102H IMR1L FFFFF102H IMR1H FFFFF103H 1 TMHMK1 IMR1 IMR1HNote IMR1L BRGM...

Page 550: ...cleared 0 when execution is returned from non maskable interrupt servicing or exception processing This register is read only in 8 bit or 1 bit units Reset sets this register to 00H Caution If an inte...

Page 551: ...gment disabled ID 0 1 Maskable interrupt servicing specificationNote After reset 00000020H Note Interrupt disable flag ID function ID is set 1 by the DI instruction and cleared 0 by the EI instruction...

Page 552: ...0 After reset 00H R W Address FFFFF6C2H Interval timer mode Generate maskable interrupt INTWDTM1 when overflow occurs Watchdog timer mode 1Note 3 Generate non maskable interrupt INTWDT1 when overflow...

Page 553: ...and INTP4 to INTP7 pins include a noise eliminator that operates using analog delay Therefore a signal input to each pin is not detected as an edge unless it maintains its input level for a certain pe...

Page 554: ...n 8 bit or 1 bit units Reset sets this register to 00H NFEN Analog noise elimination Digital noise elimination NFEN 0 1 Setting of INTP3 pin noise elimination NFC NFSTS 0 0 0 NFC2 NFC1 NFC0 Number of...

Page 555: ...6 25 6 s 51 2 s 64 s 0 0 1 1 fXX 512 51 2 s 102 4 s 128 s 0 1 0 0 fXX 1024 102 4 s 204 8 s 256 s 0 1 0 1 fXT 32 768 kHz 61 04 s 1 0 0 0 fXX 64 3 2 s 6 4 s 8 s 1 0 0 1 fXX 128 6 4 s 12 8 s 16 s 1 0 1 0...

Page 556: ...ction alternate function edge detection may be performed Therefore set the port mode after setting the INTF0n and INTR0n bits 00 0 INTR0 INTR06 INTR05 INTR04 INTR03 INTR02 INTP2 INTP1 INTP0 NMI 0 0 Af...

Page 557: ...to 00H Caution When switching to the port function from the external interrupt function alternate function edge detection may be performed Therefore set the port mode after setting the INTF31 and INTR...

Page 558: ...ternal interrupt function alternate function edge detection may be performed Therefore set the port mode after setting the INTF9n and INTR9n bits 00 INTR915 INTR9H INTR914 INTR913 0 0 0 0 0 After rese...

Page 559: ...interrupt source 4 Sets the PSW EP and PSW ID bits to 1 5 Loads the handler address 00000040H or 00000050H for the software exception routine to the PC and transfers control Figure 17 8 shows the soft...

Page 560: ...to the address of the restored PC and PSW Figure 17 9 shows the processing flow of the RETI instruction Figure 17 9 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Origin...

Page 561: ...e EP flag which is bit 6 of the PSW is a status flag that indicates that exception processing is in progress It is set when an exception occurs 0 NP EP ID SAT CY OV S Z PSW Exception processing not in...

Page 562: ...h an instruction is executed an exception trap is generated 15 16 23 22 X X X X X X 0 X X X X X X X X X X 1 1 1 1 1 1 X X X X X 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 X don t care Caution It is recommen...

Page 563: ...p processing by the DBRET instruction When the DBRET instruction is executed the CPU performs the following processing and transfers control to the address of the restored PC 1 Loads the restored PC a...

Page 564: ...s the following processing 1 Operation 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the PSW NP PSW EP and PSW ID bits to 1 4 Sets the handler address 00000060H for the debug...

Page 565: ...U performs the following processing and transfers control to the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the loaded address of the restore...

Page 566: ...ervicing control is performed when interrupts are enabled PSW ID bit 0 Even in an interrupt servicing routine multiple interrupt control must be performed while interrupts are enabled ID bit 0 If a ma...

Page 567: ...ach maskable interrupt request After reset interrupt requests are masked by the xxICn xxMKn bit and the priority is set to level 7 by the xxPRn0 to xxPRn2 bits Priorities of maskable interrupts are as...

Page 568: ...nstruction 2 Interrupt acknowledgment operation Instruction first instruction of interrupt servicing routine Interrupt request IF ID EX MEM WB IFX IDX INT1 INT2 INT3 INT4 4 system clocks 2 Maximum int...

Page 569: ...OT1 and CLR1 instructions for the following registers Interrupt related registers Interrupt control register xxlCn interrupt mask registers 0 1 3 IMR0 IMR1 IMR3 Power save control register PSC 17 10 C...

Page 570: ...o another pin Table 18 1 Assignment of Key Return Detection Pins Flag Pin Description KRM0 Controls KR0 signal in 1 bit units KRM1 Controls KR1 signal in 1 bit units KRM2 Controls KR2 signal in 1 bit...

Page 571: ...gnal Detects key return signal KRMn 0 1 Key return mode control KRM KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 After reset 00H R W Address FFFFF300H Caution If the KRM register is changed an interrupt request...

Page 572: ...the internal system clock Sub IDLE mode Mode to stop all the operations of the internal circuits except the oscillator in the subclock operation mode Internal oscillation clock operation mode Note 3 M...

Page 573: ...10 Setting of STOP mode IDLE mode Internal oscillation HALT mode HALT mode Sub IDLE mode STOP mode ResetNote 3 Interrupt requestNote 2 Setting of IDLE mode Interrupt requestNote 4 Interrupt requestNot...

Page 574: ...or unmasked internal interrupt request signal from peripheral functions operable in IDLE mode 7 RESET pin input WDTRES2 POCRES or LVIRES signal While the main clock fX is oscillating the standby mode...

Page 575: ...input disabled NMI0M 0 1 Control of releasing standby modeNote by NMI pin input Releasing standby modeNote by maskable interrupt request signals enabled Releasing standby modeNote by maskable interru...

Page 576: ...et sets this register to 00H XTSTP Subclock oscillator used Subclock oscillator not used XTSTP 0 1 Specification of subclock oscillator use PSMR 0 0 0 0 0 0 PSM IDLE mode STOP mode PSM 0 1 Specificati...

Page 577: ...92 ms 16 38 ms 32 77 ms 65 54 ms 131 1 ms 262 1 ms 524 3 ms 1 638 ms 6 554 ms 13 11 ms 26 21 ms 52 43 ms 104 9 ms 209 7 ms 419 4 ms fX After reset Note R W Address FFFFF6C0H Note This register is set...

Page 578: ...RES1 WDTRES2 POCRES LVIRES CLMRES signal After the HALT mode has been released the normal operation mode is restored 1 Releasing HALT mode by non maskable interrupt request signal or unmasked maskable...

Page 579: ...TMH0 TMH1 Operable Watch timer Operable when main clock is selected as count clock Operable Watchdog timer 1 Operable Watchdog timer 2 Operable when fR 8 is selected as count clock Operable CSI00 CSI...

Page 580: ...interrupt request signal from the peripheral functions operable in the IDLE mode or reset except WDTRES1 signal After the IDLE mode has been released the normal operation mode is restored 1 Releasing...

Page 581: ...le when fR 2048 is selected as count clock Watch timer Operable when main clock is selected as count clock Operable Watchdog timer 1 Stops operation Watchdog timer 2 Operable when fR 8 is selected as...

Page 582: ...unctions operable in the STOP mode or reset except WDTRES1 signal After the STOP mode has been released the normal operation mode is restored after the oscillation stabilization time has been secured...

Page 583: ...e when fR 2048 is selected as count clock Watch timer Stops operation Operable when fXT is selected as count clock Watchdog timer 1 Stops operation Watchdog timer 2 Operable when fR 8 is selected as c...

Page 584: ...peration performed when the STOP mode is released by an interrupt request signal is shown below Figure 19 2 Oscillation Stabilization Time Oscillated waveform Main clock oscillator stops Oscillation s...

Page 585: ...do not change the set values of the PCC CK2 to PCC CK0 bits using a bit manipulation instruction to manipulate the bit is recommended For details refer to 5 3 1 Processor clock control register PCC 2...

Page 586: ...k operation mode Timer H TMH0 Operable Stops operation Timer H TMH1 Operable Operable when fR 2048 is selected as count clock Watch timer Operable Operable when fXT is selected as count clock Watchdog...

Page 587: ...E mode or reset except WDTRES1 signal When the sub IDLE mode is released by an interrupt request signal the subclock operation mode is set If it is released by reset the normal operation mode is resto...

Page 588: ...0 Stops operation Timer H TMH1 Operable when fR 2048 is selected as count clock Watch timer Operable Operable when fXT is selected as count clock Watchdog timer 1 Stops operation Watchdog timer 2 Oper...

Page 589: ...CLM CLMRES System reset by power on clear POC POCRES Analog digital analog noise eliminator of RESET pin selectable Reset output function P00 TOH0 pin 20 2 Configuration Figure 20 1 Reset Block Diagr...

Page 590: ...generated Generated RESF 0 0 WDT2RF 0 0 CLMRF LVIRF After reset 00HNote R W Address FFFFF888H Reset signal from watchdog timer 2 WDTRES2 WDT1RF 0 1 Not generated Generated Reset signal from watchdog...

Page 591: ...me selection register OSTS and CHAPTER 25 MASK OPTION OPTION BYTE Table 20 1 Hardware Status on RESET Pin Input Item During Reset After Reset Main clock oscillator fX Oscillation stops Oscillation sta...

Page 592: ...bilization time counter Internal system reset signal active low Analog delay eliminated as noise Analog delay Eliminated as noise RESET fX fCLK Detected as reset Figure 20 3 Operation on Power Applica...

Page 593: ...n in 8 bit units Reset sets this register to 00H 0 SMPSEL 0 1 20 times 10 times RNZC 0 0 0 0 0 SMPSEL RNZSELNote After reset 00H R W Address FFFFF860H Selection of number of samplings RNZSELNote 0 1 A...

Page 594: ...cted input to the RESET signal is not received Therefore only the analog noise eliminator is automatically selected Only the analog noise eliminator is automatically selected during the following peri...

Page 595: ...le 20 3 Hardware Status on Occurrence of WDTRES1 Signal Item During Reset After Reset Main clock oscillator fX Oscillation continues Subclock oscillator fXT Oscillation continues Internal oscillator f...

Page 596: ...ng the reset period the oscillation stabilization time must be secured The oscillation stabilization time is determined by the default value of the OSTS register for the oscillation stabilization time...

Page 597: ...e Status During Reset Operation by Power on Clear Item During Reset After Reset Main clock oscillator fX Oscillation stops Oscillation starts Subclock oscillator fXT Oscillation continues Internal osc...

Page 598: ...Reset Timing by Power on Clear Circuit Oscillation stabilization time count Initialized to fXX 8 operation Overflow of oscillation stabilization time counter Internal system reset signal active low P...

Page 599: ...igure 20 8 Reset Timing on Power Application Oscillation stabilization time count Initialized to fXX 8 operation Overflow of oscillation stabilization time counter Internal system reset signal active...

Page 600: ...he main clock oscillator stops during the reset period the oscillation stabilization time must be secured The oscillation stabilization time is determined by the default value of the OSTS register for...

Page 601: ...Reset After Reset Main clock oscillator fX Oscillation stops Oscillation remains stopped Subclock oscillator fXT Oscillation continues Internal oscillator fR Oscillation stops Oscillation starts Perip...

Page 602: ...ode PM0 PM00 bit 0 and outputs a low level P0 P00 bit 0 when the reset signal is generated To release the reset output low level output high level output set the P00 bit to 1 by software Figure 20 10...

Page 603: ...it 1 when subclock operates and PCC CLS bit 0 when main clock operates When the sampling clock internal oscillation clock is stopped When the CPU operates on internal oscillation clock 21 2 Registers...

Page 604: ...bit or 1 bit units Reset sets this register 00H 0 RCM 0 0 0 0 0 0 RSTOP Internal oscillator oscillating Internal oscillator stopped RSTOP 0 1 Oscillation stop of internal oscillator After reset 00H R...

Page 605: ...Internal Oscillation Clock Status of Clock Monitor Normal operation mode Oscillates Oscillates Note 1 Operates Note 2 HALT mode Oscillates Oscillates Note 1 Operates Note 2 IDLE mode Oscillates Oscill...

Page 606: ...ode is released If the STOP mode is set when the CLME bit 1 the monitor operation is stopped in the STOP mode and while the oscillation stabilization time is being counted The monitor operation is aut...

Page 607: ...s operating Figure 21 3 Operation When Main Clock Is Stopped Arbitrary Clock monitor status During monitoring Monitor stops Monitor stops During monitoring CLME bit Internal oscillation clock Main clo...

Page 608: ...to 4 369 ms Watchdog timer 2 overflow time After STOP mode release by interrupt WDTM2 2 12 fR to 2 19 fR 8 5 ms to 34 1 ms MIN 1 092 ms to 4 369 ms MAX Note The oscillation stabilization time can be...

Page 609: ...ation time secured count operation stops Main clock operation stopped Watchdog timer 2 overflow WDTRES2 does not occur Watchdog timer 2 count operation starts Main clock stop detected Program fetch st...

Page 610: ...illation clock operation mode Timer H TMH0 Stops operation Timer H TMH1 Operable when fR 2 048 is selected as count clock Watch timer Stops operation Operable when fXT is selected as count clock Watch...

Page 611: ...ignal the internal oscillation clock operation mode is set When the internal oscillation HALT mode is released by reset the normal operation mode is restored if the main clock fX oscillates correctly...

Page 612: ...ted as count clock or when INTTM010 is selected as count clock and TM01 is enabled in internal oscillation HALT mode Timer H TMH0 Stops operation Timer H TMH1 Operable when fR 2048 is selected as coun...

Page 613: ...re Operable in STOP mode When the low voltage detector is used to reset the RESF LVIRF bit is set to 1 if the LVIRES signal is generated For details of the RESF register refer to 20 3 1 Reset source f...

Page 614: ...than the low voltage detector The LVIM register holds its value when reset is effected by the low voltage detector LVION LVION 0 1 Disable operation Enable operation LVIM 0 0 0 0 0 LVIMD LVIFNote 2 Af...

Page 615: ...ated The LVIS register is reset to 00H by a reset source other than the low voltage detector The LVIS register holds its value when reset is effected by the low voltage detector 0 LVIS2 0 0 0 0 1 1 1...

Page 616: ...voltage VLVI using the LVIS LVIS2 to LVIS LVIS0 bits 3 Set the LVIM LVION bit to 1 enables low voltage detector operation 4 Use software to instigate a wait of at least 0 2 ms 5 Confirm that the LVIM...

Page 617: ...is set to 1 use software to instigate a wait until the LVIF bit is cleared to 0 6 Clear the INTLVI interrupt request flag LVIIF bit to 0 7 Release the INTLVI interrupt mask status LVIMK bit 0 Caution...

Page 618: ...ply voltage VDD and detection voltage VPOC and generates a reset signal POCRES when VDD VPOC detection voltage VPOC 2 6 V 0 1 V Caution If the POCRES signal is generated by the POC circuit the RESF re...

Page 619: ...The power on clear circuit compares the supply voltage VDD and detection voltage VPOC and generates a reset signal POCRES when VDD VPOC Figure 23 2 Operation of Power on Clear Circuit Supply voltage...

Page 620: ...RAM By using this function program bugs found in the internal ROM can be corrected Up to four addresses can be specified for correction Figure 24 1 Block Diagram of ROM Correction Instruction address...

Page 621: ...lower 16 bits as the CORADnL register these registers can be read or written in 16 bit units Reset sets these registers to 00000000H Set correction addresses in the range of 0000000H to 001FFFEH in t...

Page 622: ...he fetch address of the internal ROM match the fetch code is replaced by the DBTRAP instruction 2 When the DBTRAP instruction is executed execution branches to address 00000060H 3 Software processing...

Page 623: ...on code address of corresponding channel n Execute fetch code Read data for setting ROM correction from external memory Execute DBTRAP instruction Jump to address 00000060H Execute correction code Exe...

Page 624: ...ing invalid by software Depending on whether the option to enable disable stopping of internal oscillator by software is set or not the operation differs as follows Table 25 1 Option to Enable Disable...

Page 625: ...up resistor option The option byte is stored in address 000007AH of the internal flash memory internal ROM area as 8 bit data OSTS0Note 1 Shorten oscillation stabilization time default value of OSTS r...

Page 626: ...owing development environments and mass production applications For altering software after the V850ES KE1 is soldered onto the target system For data adjustment when starting mass production For diff...

Page 627: ...Figure 26 1 Flash Memory Mapping Block 0 2 KB Block 1 2 KB Block 2 2 KB Block 3 2 KB Block 5 2 KB Block 6 2 KB Block 7 2 KB Block 8 2 KB Block 4 2 KB Block 63 2 KB 00007FFH 0000800H 0000FFFH 0001000H...

Page 628: ...programming so that the flash memory can be rewritten under various conditions such as while communicating with an external device Table 26 1 Rewrite Method Rewrite Method Functional Outline Operatio...

Page 629: ...ter shipment and security can be set by rewriting via on board off board programming Each security function can be used in combination with the others at the same time Table 26 3 Security Functions Fu...

Page 630: ...command prohibit Block erase command Chip erase command Note 1 Program command Read command Block erase FlashBlockErase Chip erase Writing FlashWordWrite Reading FlashWordRead Setting of prohibition...

Page 631: ...ermore similar to the mask ROM products when program rewriting is not necessary additionally disable the chip erase command Disable Chip Erase Notes 1 Set Supply voltage Program download upload and Co...

Page 632: ...nt required for writing programs to the flash memory of the V850ES KE1 Figure 26 2 Environment Required for Writing Programs to Flash Memory Host machine RS 232C Dedicated flash programmer V850ES KE1...

Page 633: ...ogrammer UART0 Dedicated flash programmer V850ES KE1 VDD VSS RESET TXD0 RXD0 FLMD1 FLMD1 FLMD0 FLMD0 VDD GND RESET RxD TxD X1 X2 CLK PG FP4 Flash Pro4 Cxxxxxx Bxxxxx Axxxx XXX YYY XXXXX XXXXXX XXXX XX...

Page 634: ...Connections of Dedicated Flash Programmer PG FP4 PG FP4 V850ES KE1 Processing for Connection Signal Name I O Pin Function Pin Name UART0 CSI00 CSI00 HS FLMD0 Output Write enable disable FLMD0 FLMD1 Ou...

Page 635: ...eded X1 X1 7 X1 7 X1 7 CLK Output Clock to V850ES KE1 X2 X2Note 8 X2Note 8 X2Note 8 RESET Output Reset signal RESET RESET 9 RESET 9 RESET 9 FLMD0 Input Write voltage FLMD0 FLMD0 3 FLMD0 3 FLMD0 3 FLMD...

Page 636: ...A 64GK 9ET A FA 64GB 8EU A 1 2 VD D G N D G N D V D D G N D VD D V D D G N D 32 1 7 6 2 33 45 52 Note 1 19 20 21 23 22 8 9 4 3 J1 VDD2 VDD SO SCK SI RESET VPP RESERVE HS CLKOUT SO SCK SI X1 X2 RESET C...

Page 637: ...to CLKIN of FA Connect X1 of FA to X1 of the device Connect X2 of FA to X2 of the device If an oscillator is created on the flash adapter and a clock is supplied the above setting and connections wil...

Page 638: ...memory control The following shows the procedure for manipulating the flash memory Figure 26 7 Procedure for Manipulating Flash Memory Start Select communication system Manipulate flash memory End Yes...

Page 639: ...D0 input RXD0 input TXD0 output VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Note Power on Oscillation stabilized Communication mode selected Flash control command communication erasure write etc Reset...

Page 640: ...g corresponding to the commands Table 26 7 Flash Memory Control Commands Support Classification Command Name CSI00 CSI00 HS UART0 Function Blank check Block blank check command Checks if the contents...

Page 641: ...refore pin handling is required when the external device does not acknowledge the status immediately after a reset 1 FLMD0 pin In the normal operation mode input a voltage of VSS level to the FLMD0 pi...

Page 642: ...e connection of the FLMD1 pin Figure 26 11 FLMD1 Pin Connection Example FLMD1 Pull down resistor RFLMD1 Other device V850ES KE1 Caution If the VDD signal is input to the FLMD1 pin from another device...

Page 643: ...Conflict of signals When the dedicated flash programmer output is connected to a serial interface pin input that is connected to another device output a conflict of signals occurs To avoid the conflic...

Page 644: ...connection to the other device Figure 26 13 Malfunction of Other Device V850ES KE1 Pin Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode if the sig...

Page 645: ...nal generator Conflict of signals Output pin In the flash memory programming mode the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs Therefo...

Page 646: ...ming library that is used to rewrite the flash memory with a user application program the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external mem...

Page 647: ...ck 4 Block 3 Block 2 Block 1 Block 0 Block 63 Block 63 Boot swap Rewriting boot areas 0 and 1 Block 8 Block 7 Block 6 Block 5 Block 4 Block 3 Block 2 Block 1 Block 0 Block 8 Block 7 Block 6 Block 5 Bl...

Page 648: ...manipulation End of processing Flash environment initialization processing Erase processing Write processing Flash information setting processingNote 1 Internal verify processing Boot area swapping pr...

Page 649: ...e Power Supply Flash Memory User s Manual Contact an NEC Electronics sales representative for the above manual 26 5 5 Pin processing 1 FLMD0 pin The FLMD0 pin is used to set the operation mode when re...

Page 650: ...Can be used in user application execution status or self programming status To use this interrupt in the self programming status since the processing transits to the address of the internal RAM start...

Page 651: ...Set the ID code in the 10 byte on chip flash memory area from 0000070H to 0000079H to allow the debugger perform ID authentication If the IDs match the security is released and reading flash memory an...

Page 652: ...in Table 27 1 the ID code input in the configuration dialog box of the ID850QB is 123456789ABCDEF123D4 Table 27 1 ID Code Address Value 0x70 0x12 0x71 0x34 0x72 0x56 0x73 0x78 0x74 0x9A 0x75 0xBC 0x7...

Page 653: ...he mask function the I O buffer port pin may be reset if a reset signal is input from a pin 3 Because a software breakpoint set in the internal flash memory is realized by the ROM correction function...

Page 654: ...temperature TA Flash memory programming mode 40 to 85 C PD703302 703302Y 65 to 150 C Storage temperature Tstg PD70F3302 70F3302Y 40 to 125 C Notes 1 Be sure not to exceed the absolute maximum ratings...

Page 655: ...ting Conditions TA 40 to 85 C VDD EVDD AVREF0 2 7 to 5 5 V VSS EVSS AVSS 0 V CL 50 pF Parameter Symbol Conditions MIN TYP MAX Unit VDD 4 5 to 5 5 V 0 25 20 MHz VDD 4 0 to 5 5 V 0 25 16 MHz In PLL mode...

Page 656: ...5 5 V 0 25 12 MHz In PLL mode VDD 2 7 to 5 5 V 0 25 6 MHz VDD 4 0 to 5 5 V 0 0625 10 MHz In clock through mode VDD 2 7 to 5 5 V 0 0625 6 MHz Internal system clock frequency fCLK Operating with subclo...

Page 657: ...0 V Recommended Circuit Parameter Conditions MIN TYP MAX Unit VDD 4 5 to 5 5 V 2 5 MHz VDD 4 0 to 5 5 V 2 4 MHz PLL mode VDD 2 7 to 5 5 V 2 2 5 MHz External clock X2 X1 Input frequency fX Note Clock t...

Page 658: ...effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuat...

Page 659: ...3 to P915 PCM0 PCM1 PDL0 to PDL7 10 mA EVDD 4 0 to 5 5 V 15 mA Per pin for P38 P39 EVDD 2 7 to 5 5 V 8 mA Total of P00 to P06 P30 to P35 P40 to P42 30 mA Output current low IOL1 Total of P38 P39 P50 t...

Page 660: ...t leakage current high ILOH VO VDD 3 0 A Output leakage current low ILOL VO 0 V 3 0 A Pull up resistor RL VIN 0 V 10 30 100 k Notes 1 Total of P00 to P06 P30 to P35 P40 to P42 and their alternate func...

Page 661: ...IDD4 Subclock operation mode fXT 32 768 kHz Main oscillation stopped internal oscillator stopped 240 400 A IDD5 Sub IDLE mode fXT 32 768 kHz Watch timer operating main oscillation stopped internal osc...

Page 662: ...V 10 1 4 2 3 mA IDD3 fX 10 MHz in clock through mode VDD 3 V 10 1 0 1 7 mA IDD4 Subclock operation mode fXT 32 768 kHz Main oscillation stopped internal oscillator stopped 90 200 A IDD5 Sub IDLE mode...

Page 663: ...R STOP mode 2 0 5 5 V STOP release signal input time tDREL 0 s Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated operating range tDREL STOP release signal i...

Page 664: ...ints Load Conditions VOH VOL VOH VOL Measurement points EVDD EVSS DUT Device under measurement CL 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration bring the load ca...

Page 665: ...itions MIN MAX Unit Output cycle tCYK 1 50 ns 30 6 s VDD 4 0 to 5 5 V tCYK 2 17 ns High level width tWKH 2 VDD 2 7 to 5 5 V tCYK 2 26 ns VDD 4 0 to 5 5 V tCYK 2 17 ns Low level width tWKL 3 VDD 2 7 to...

Page 666: ...low level width tWITL 92 n 3 when digital noise elimination selected Ni tISMP 200 ns VDD 4 0 to 5 5 V T 50 ns ADTRG high level width tWADH 93 VDD 2 7 to 5 5 V T 100 ns VDD 4 0 to 5 5 V T 50 ns ADTRG...

Page 667: ...IPL 100 VDD 2 7 to 5 5 V np Tsmpp 200 Note 2 ns Notes 1 Tsmp0 Timer 0 count clock cycle However Tsmp0 4 fXX when TI010 is used as an external event count input 2 np Number of sampling clocks set by th...

Page 668: ...2 7 to 5 5 V 50 ns VDD 4 0 to 5 5 V 30 ns Delay time from SCK0n to SO0n output tKSO1 105 VDD 2 7 to 5 5 V 60 ns Remark n 0 1 2 Slave mode TA 40 to 85 C VDD EVDD AVREF0 2 7 to 5 5 V VSS EVSS AVSS 0 V C...

Page 669: ...ming a CSICn CKPn CSICn DAPn bits 00 or 11 SO0n output Input data Output data SI0n input SCK0n I O 101 102 102 103 104 105 Hi Z Hi Z b CSICn CKPn CSICn DAPn bits 01 or 10 SO0n output Input data Output...

Page 670: ...setup time tSU STO 120 4 0 0 6 s Pulse width of spike suppressed by input filter tSP 121 0 50 ns Capacitance load of each bus line Cb 400 400 pF Notes 1 At the start condition the first clock pulse i...

Page 671: ...PECIFICATIONS User s Manual U16896EJ2V0UD 671 I 2 C Bus Mode PD703302Y 70F3302Y Only Stop condition Start condition Restart condition Stop condition SCL0 I O SDA0 I O 113 119 119 118 118 116 117 115 1...

Page 672: ...0 100 s Conversion time tCONV 2 7 AVREF0 2 85 V Normal mode 17 0 100 s 4 0 AVREF0 5 5 V 0 4 FSR Zero scale error Note 1 EZS 2 7 AVREF0 4 0 V 0 6 FSR 4 0 AVREF0 5 5 V 0 4 FSR Full scale error Note 1 E...

Page 673: ...e 1 tPTHD 123 After voltage reaches detection voltage MAX on power application 3 0 ms Response time 2 Note 2 tPD 124 When power supply drops 1 0 ms Minimum pulse width tPW 125 0 2 ms Notes 1 Time from...

Page 674: ...s 100 3 3 3 5 3 7 V LVIS LVIS2 to LVIS LVIS0 bits 101 3 15 3 3 3 45 V Detection voltage VLVI LVIS LVIS2 to LVIS LVIS0 bits 110 2 95 3 1 3 25 V Response time Note 1 tLD 126 0 2 2 0 ms Minimum pulse wid...

Page 675: ...initially to shipped products it is also counted as one rewrite for write only Example P Write E Erase Shipped product P E P E P 3 rewrites Shipped product E P E P E P 3 rewrites 2 Serial write opera...

Page 676: ...C 12 0 0 2 D F 1 125 14 0 0 2 B 12 0 0 2 N 0 10 P Q 0 1 0 05 1 0 S R 3 4 3 R H K J Q G I S P detail of lead end NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum...

Page 677: ...STIC LQFP 10x10 ITEM MILLIMETERS A B D G 12 0 0 2 10 0 0 2 1 25 12 0 0 2 H 0 22 0 05 C 10 0 0 2 F 1 25 I J K 0 08 0 5 T P 1 0 0 2 L 0 5 P 1 4 Q 0 1 0 05 T 0 25 S 1 5 0 10 U 0 6 0 15 S64GB 50 8EU 2 R 3...

Page 678: ...Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 60 seconds max at 220 C or higher Count Three times or less Exposure limit 7 days Note after that prebake at 125 C for...

Page 679: ...kage peak temperature 260 C Time 60 seconds max at 220 C or higher Count Three times or less Exposure limit 7 days Note after that prebake at 125 C for 20 to 72 hours IR60 207 3 Partial heating Pin te...

Page 680: ...velopment tool configuration Support for PC98 NX series Unless otherwise specified products supported by IBM PC ATTM compatibles are compatible with PC98 NX series computers When using PC98 NX series...

Page 681: ...or conversion adapter Target system Flash programmer Flash memory write adapter Flash memory Project manager Windows only Note 1 Software package Control software Embedded software Real time OS Netwo...

Page 682: ...DA Conversion socket or conversion adapter Target system Flash programmer Flash memory write adapter Flash memory Project manager Windows only Note 1 Software package Control software Embedded softwa...

Page 683: ...vice file This file contains information peculiar to the device This device file should be used in combination with a tool CA850 and ID850QB The corresponding OS and host machine differ depending on t...

Page 684: ...5 6 7 8 9 10 11 12 13 Option products 1 Host machine PC 9821 series PC AT compatibles 2 Debugger USB driver manuals etc ID850QB Disk Accessory Disk Note 1 3 USB interface cable 4 AC adapter 5 In circu...

Page 685: ...ith a power supply unit and emulation probe Use USB to connect this emulator to the host machine 3 USB interface cable Cable to connect the host machine and the QB V850ESKX1H 4 AC adapter 100 to 240 V...

Page 686: ...guration when connecting the MINICUBE and the debug adapter QB V850ESKX1H DA to the host machine PC 9821 series PC AT compatible is shown below If no option products are prepared connection is possibl...

Page 687: ...0 cm 6 QB V850ESKX1H DA Debug adapter This operates as an in circuit emulator by using in combination with MINICUBE This is provided with MINICUBE 7 QB 64 CA 01S option Check pin adapter Adapter used...

Page 688: ...th the source program using an integrating window function that associates the source program disassemble display and memory display with the trace result It should be used in combination with the dev...

Page 689: ...mark and in the part number differ depending on the host machine and OS used S RX703000 S RX703100 Product Outline Maximum Number for Use in Mass Production 001 Evaluation object Do not use for mass p...

Page 690: ...regID System register number vector 5 bit data that specifies the trap vector 00H to 1FH cccc 4 bit data that shows the condition codes sp Stack pointer r3 ep Element pointer r30 listX X item registe...

Page 691: ...FH n 80000000H let it be 80000000H result Reflects the results in a flag Byte Byte 8 bits Halfword Halfword 16 bits Word Word 32 bits Addition Subtraction ll Bit concatenation Multiplication Division...

Page 692: ...la Explanation 0000 OV 1 Overflow 1000 OV 0 No overflow 0001 CY 1 Carry Lower Less than 1001 CY 0 No carry Not lower Greater than or equal 0010 Z 1 Zero 1010 Z 0 Not zero 0011 CY or Z 1 Not higher Les...

Page 693: ...ww01101000000 GR reg3 GR reg2 7 0 ll GR reg2 15 8 ll GR reg2 23 16 ll GR reg2 31 24 1 1 1 0 CALLT imm6 0 0 0 0 0 0 1 0 0 0 i i i i i i CTPC PC 2 return PC CTPSW PSW adr CTBP zero extend imm6 logically...

Page 694: ...reg2 rrrrr000010RRRRR GR reg2 GR reg2 GR reg1 Note 6 35 35 35 DIVH reg1 reg2 reg3 rrrrr111111RRRRR wwwww01010000000 GR reg2 GR reg2 GR reg1 Note 6 GR reg3 GR reg2 GR reg1 35 35 35 DIVHU reg1 reg2 reg...

Page 695: ...rrrrr110010RRRRR i i i i i i i i i i i i i i i i GR reg2 GR reg1 imm16 ll 016 1 1 1 reg1 reg2 reg3 rrrrr111111RRRRR wwwww01000100000 GR reg3 ll GR reg2 GR reg2 xGR reg1 Note 14 1 4 5 MUL imm9 reg2 reg...

Page 696: ...W else if PSW NP 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW 3 3 3 R R R R R reg1 reg2 rrrrr111111RRRRR 0000000010100000 GR reg2 GR reg2 arithmetically shift right by GR reg1 1 1 1 0 SAR imm5 reg2...

Page 697: ...p zero extend disp4 GR reg2 zero extend Load memory adr Byte 1 1 Note9 SLD H disp8 ep reg2 rrrrr1000ddddddd Note 19 adr ep zero extend disp8 GR reg2 sign extend Load memory adr Halfword 1 1 Note9 SLD...

Page 698: ...3 Note3 TST1 reg2 reg1 rrrrr111111RRRRR 0000000011100110 adr GR reg1 Z flag Not Load memory bit adr reg2 3 Note3 3 Note3 3 Note3 XOR reg1 reg2 rrrrr001001RRRRR GR reg2 GR reg2 XOR GR reg1 1 1 1 0 XORI...

Page 699: ...ication 13 i i i i i Lower 5 bits of imm9 I I I I Higher 4 bits of imm9 14 Do not specify the same register for general purpose registers reg1 and reg3 15 sp imm specified by bits 19 and 20 of the sub...

Page 700: ...T 425 CKSR1 Clock select register 1 UART 425 CLM Clock monitor mode register CLM 603 CMP00 8 bit timer H compare register 00 TMH 314 CMP01 8 bit timer H compare register 01 TMH 315 CMP10 8 bit timer H...

Page 701: ...I 2 C 472 IICIC0 Interrupt control register INTC 548 IICS0 IIC status register 0 I 2 C 469 IICX0 IIC function expansion register 0 I 2 C 475 IMR0 Interrupt mask register 0 INTC 549 IMR0H Interrupt mas...

Page 702: ...Port 3 function control register Port 83 PFC5 Port 5 function control register Port 89 PFC9 Port 9 function control register Port 95 PFC9H Port 9 function control register H Port 95 PFC9L Port 9 func...

Page 703: ...tatus word CPU 46 PU0 Pull up resistor option register 0 Port 79 PU3 Pull up resistor option register 3 Port 84 PU4 Pull up resistor option register 4 Port 86 PU5 Pull up resistor option register 5 Po...

Page 704: ...l transmit buffer register 0L CSI0 442 SOTBF1 Clocked serial interface initial transmit buffer register 1 CSI0 442 SOTBF1L Clocked serial interface initial transmit buffer register 1L CSI0 442 SREIC0...

Page 705: ...0IOC0 TMP0 I O control register 0 TMP 141 TP0IOC1 TMP0 I O control register 1 TMP 142 TP0IOC2 TMP0 I O control register 2 TMP 143 TP0OPT0 TMP0 option register 0 TMP 144 TP0OVIC Interrupt control regis...

Page 706: ...nt count mode p 170 Modification of Figure 6 17 Basic Timing in External Trigger Pulse Output Mode p 170 Partial addition of description to 6 5 3 External trigger pulse output mode TP0MD2 to TP0MD0 bi...

Page 707: ...n ASISn p 404 Addition of Caution 2 to 14 3 6 LIN operation control register 0 ASICL0 p 405 Addition of Cautions 1 to 6 to 14 3 6 LIN operation control register 0 ASICL0 p 422 Modification of 14 5 8 2...

Page 708: ...ification of Table 21 5 Operation Status in Internal Oscillation HALT Mode p 624 Partial addition to Table 25 1 Option to Enable Disable Stopping of Internal Oscillator by Software p 629 Modification...

Page 709: ...wan R O C Tel 02 8175 9600 http www tw necel com NEC Electronics Singapore Pte Ltd 238A Thomson Road 12 08 Novena Square Singapore 307684 Tel 6253 8311 http www sg necel com For further information pl...

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