CHAPTER 14 ASYNCHRONOUS SERIAL INTERFACE (UART)
User’s Manual U16896EJ2V0UD
421
Figure 14-13. LIN Reception Manipulation Outline
Reception interrupt (INTUAnR)
Edge detection
Capture timer
Disable
Disable
Enable
RXD0 (input)
Enable
<2>
13 bits
SBF
reception
<3>
<4>
<1>
SF reception
ID reception
Data
transmission
Data
transmission
<5>
Data transmission
LIN bus
Wakeup
signal frame
Sync
break field
Sync
field
Ident
field
Data
field
Data
field
Checksum
field
<1> The wakeup signal is sent by the pin edge detector. UART0 is enabled and the SBF reception mode is
set using the wakeup signal.
<2> The receive operation is performed until detection of the stop bit. Upon detection of SBF reception of 11
or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon detection of
SBF reception of less than 11 bits, an SBF reception error is judged, no interrupt signal is output, and the
mode returns to the SBF reception mode.
<3> If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF
reception completion interrupt. Moreover, error detection for the ASIS0.PE0, ASIS0.FE0, and
ASIS0.OVE0 bits is suppressed and UART communication error detection processing and data transfer
of the receive shift register and RXB0 register are not performed. The receive shift register holds the
initial value, FFH.
<4> The RXD0 pin is connected to TI (capture input: refer to
14.3 (7) Selector operation control register 0
(SELCNT0)
) of the timer, the transfer rate is calculated, and the baud rate error is calculated. The value
of BRG (refer to
14.6 Dedicated Baud Rate Generator n (BRGn)
) obtained by correcting the baud rate
error after dropping UART0 enable is set again, causing the status to become the reception status.
<5> Checksum field distinctions are made by software. UART0 is initialized following CSF reception, and the
processing for setting the SBF reception mode again is performed by software.
