CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0
User’s Manual U16896EJ2V0UD
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(4) Data hold timing of capture register
(a) If the valid edge of the TI011/TI010 pin is input while the CR010/CR011 register is read, the CR010/CR011
register performs capture operation, but the read value at this time is not guaranteed. However, the interrupt
request signal (INTTM010/INTTM011) is generated as a result of detection of the valid edge.
Figure 7-47. Data Hold Timing of Capture Register
N
N + 1
N + 2
X
N + 1
M
M + 1
M + 2
Count pulse
TM01 count value
Edge input
INTTM011
Value captured to CR011
Capture read signal
Capture operation is performed
but read value is not guaranteed.
Capture operation
(b) The values of the CR010 and CR011 registers are not guaranteed after 16-bit timer/event counter 01 has
stopped.
(5) Setting valid edge
Set the valid edge of the TI010 pin while the timer operation is stopped (TMC01.TMC013 and TMC01.TMC012
bits = 00). Set the valid edge by using the PRM01.ES100 and PRM01.ES101 bits.
(6) Re-triggering one-shot pulse
Make sure that the trigger is not generated while an active level is being output in the one-shot pulse output mode.
Be sure to input the next trigger after the current active level is output.
