NEC V850ES/KE1+, User Manual

Page: 476 / 709

CHAPTER 16 I
2
C BUS
User’s Manual U16896EJ2V0UD
476
Table 16-2. Selection Clock Setting
IICX0 IICCL0
Bit 0 Bit 3 Bit 1 Bit 0
CLX0 SMC0 CL01 CL00
Selection Clock Transfer Clock
(f
XX
/m)
Settable Internal System
Clock Frequency (f
XX
)
Range
Operation Mode
0 0 0 0 f
XX
/2 f
XX
/88 4.0 MHz to 8.38 MHz
0 0 0 1 f
XX
/2 f
XX
/172 8.38 MHz to 16.76 MHz
0 0 1 0 f
XX
f
XX
/86 4.19 MHz to 8.38 MHz
0 0 1 1 f
XX
/3 f
XX
/198 16.0 MHz to 19.8 MHz
Normal mode
(SMC0 bit = 0)
0 1 0 x f
XX
/2 f
XX
/48 8 MHz to 16.76 MHz
0 1 1 0 f
XX
f
XX
/24 4 MHz to 8.38 MHz
0 1 1 1 f
XX/
3 f
XX
/54 16 MHz to 20 MHz
High-speed mode
(SMC0 bit = 1)
1 0 x x Setting prohibited
1 1 0 x f
XX
/2 f
XX
/24 8.00 MHz to 8.38 MHz
1 1 1 0 f
XX
f
XX
/12 4.00 MHz to 4.19 MHz
High-speed mode
(SMC0 bit = 1)
1 1 1 1 Setting prohibited
Remark x: don’t care
(7) IIC shift register 0 (IIC0)
The IIC0 register is used for serial transmission/reception (shift operations) that is synchronized with the serial
clock.
The IIC0 register can be read or written in 8-bit units, but data should not be written to the IIC0 register during
a data transfer.
Access (read/write) the IIC0 register only during the wait period. Accessing this register in communication
states other than the wait period is prohibited. However, for the master device, the IIC0 register can be written
once only after the transmission trigger bit (IICC0.STT0 bit) has been set to 1.
When the IIC0 register is written during wait, the wait is cancelled and data transfer is started.
Reset sets this register to 00H.
After reset: 00H R/W Address: FFFFFD80H
7 6 5 4 3 2 1 0
IIC0
(8) Slave address register 0 (SVA0)
The SVA0 register holds the I
2
C bus’s slave addresses.
The SVA0 register can be read or written in 8-bit units, but bit 0 should be fixed as 0. However, rewriting this
register is prohibited when the IICS0.STD0 bit = 1 (start condition detection).
Reset sets this register to 00H.
After reset: 00H R/W Address: FFFFFD83H
7 6 5 4 3 2 1 0
SVA0 0
<R>
<R>