CHAPTER 13 A/D CONVERTER
User’s Manual U16896EJ2V0UD
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(5) Power fail comparison threshold register (PFT)
The PFT register sets the comparison value in the power fail detection mode.
The 8-bit data set in the PFT register is compared with the value of the ADCRH register.
The PFT register can be read or written in 8-bit units.
Reset sets this register to 00H.
PFT
After reset: 00H R/W Address: FFFFF203H
7
6
5
4
3
2
1
0
Cautions 1. Writing the PFT register is prohibited during A/D conversion operation
(ADM.ADCS bit = 1) in the normal mode (ADM.ADHS1, ADM.ADHS0 bits
= 00).
2. Accessing the PFT register is prohibited in the following statuses. For
details, refer to 3.4.8 (1) (b) Access to special on-chip peripheral I/O
register.
•
When the CPU operates on the subclock and the main clock
oscillation is stopped
•
When the CPU operates on the internal oscillation clock
<R>
<R>
