CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U16896EJ2V0UD
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When the TP0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
with the count clock, and the counter starts counting. At this time, the output of the TOP00 pin is inverted. Additionally,
the set value of the TP0CCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
cleared to 0000H, the output of the TOP00 pin is inverted, and a compare match interrupt request signal
(INTTP0CC0) is generated.
The interval can be calculated by the following expression.
Interval = (Set value of TP0CCR0 re 1)
×
Count clock cycle
Figure 6-4. Register Setting for Interval Timer Mode Operation (1/2)
(a) TMP0 control register 0 (TP0CTL0)
0/1
0
0
0
0
TP0CTL0
Select count clock
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TP0CKS2 TP0CKS1 TP0CKS0
TP0CE
(b) TMP0 control register 1 (TP0CTL1)
0
0
0/1
Note
0
0
TP0CTL1
0, 0, 0:
Interval timer mode
0: Operate on count clock
selected by TP0CKS0
to TP0CKS2 bits
1: Count with external event
count input signal
0
0
0
TP0MD2 TP0MD1 TP0MD0
TP0EEE
TP0EST
Note
This bit can be set to 1 only when the interrupt request signals (INTTP0CC0 and INTTP0CC1) are
masked by the interrupt mask flags (TP0CCMK0 and TP0CCMK1) and timer output (TOP01) is used.
However, set the TP0CCR0 and TP0CCR1 registers to the same value (refer to
6.5.1 (2) (d) Operation
of TP0CCR1 register
).
<R>
<R>
