NEC V850ES/KE1+, User Manual

Page: 314 / 709

CHAPTER 9 8-BIT TIMER H
User’s Manual U16896EJ2V0UD
314
The block diagram of 8-bit timer Hn is shown below.
Figure 9-1. Block Diagram of 8-Bit Timer Hn
Match
Selector
Internal bus
TMHEn CKSHn2 CKSHn1 CKSHn0 TMMDn1TMMDn0 TOLEVn TOENn
Decoder
8-bit timer H compare
register n0 (CMPn0)
Reload/
interrupt
control
TOHn
INTTMHn
INTTM5n
Selector
RMCn NRZBn
f
XX
f
XX
/2
f
XX
/2
2
f
XX
/2
4
f
XX
/2
6
Note
Interrupt
generator
Output
controller
Level
inversion
NRZn
1
0
F/F
R
8-bit timer
counter Hn
Carrier generator mode signal
PWM mode signal
Timer H enable signal
Clear
3
2
8-bit timer H compare
register n1 (CMPn1)
8-bit timer H mode
register n (TMHMDn)
8-bit timer H carrier control
register n (TMCYCn)
Note f
XX
/2
10
when n = 0, f
R/
2
11
when n = 1
Remark n = 0, 1
(1) 8-bit timer H compare register n0 (CMPn0)
This CMPn0 register can be read or written in 8-bit units. This register is used in all of the timer operation
modes.
This register constantly compares the value set to the CMPn0 register with the count value of 8-bit timer
counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the
output level of the TOHn pin.
Rewrite the value of the CMPn0 register while the timer is stopped (TMHMDn.TMHEn bit = 0).
Reset sets this register to 00H.
CMPn0
(n = 0, 1)
After reset: 00H R/W Address: CMP00 FFFFF582H, CMP10 FFFFF592H
7 6 5 4 3 2 1 0
Caution Rewriting the CMPn0 register during timer count operation is prohibited.
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