NEC V850ES/KE1+, User Manual

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CHAPTER 20 RESET FUNCTION
User’s Manual U16896EJ2V0UD
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20.4 Reset Sources
The following six reset sources are available.
•
Reset by RESET pin input
•
Reset by watchdog timer 1 overflow (WDTRES1)
•
Reset by watchdog timer 2 overflow (WDTRES2)
•
System reset by low-voltage detector (LVI) (LVIRES)
•
System reset by clock monitor (CLM) (CLMRES)
•
System reset by power-on-clear (POC) (POCRES)
20.4.1 Reset operation via RESET pin
When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized.
The RESET pin has a noise eliminator that can eliminate analog noise or d analog noise, depending on the
setting of the RNZC register.
While a low level is being input to the RESET pin, the main clock oscillator stops. Therefore, the overall power
consumption of the system can be reduced.
When the level of the RESET pin is changed from low to high, the reset status is released.
If the reset status is released by RESET pin input, the oscillation stabilization time elapses and then the CPU starts
program execution (for the oscillation stabilization time, refer to 19.2 (3) Oscillation stabilization time selection
register (OSTS) and CHAPTER 25 MASK OPTION/OPTION BYTE ).
Table 20-1. Hardware Status on RESET Pin Input
Item During Reset After Reset
Main clock oscillator (f
X
) Oscillation stops Oscillation starts
Subclock oscillator (f
XT
) Oscillation continues
Internal oscillator (f
R
) Oscillation stops Oscillation starts
Peripheral clock (f
XX
to f
XX
/1024) Operation stops Operation starts after securing oscillation
stabilization time
Internal system clock (f
CLK
) Operation stops Operation starts after securing oscillation
stabilization time (initialized to f
XX
/8)
CPU clock (f
CPU
) Operation stops Operation starts after securing oscillation
stabilization time (initialized to f
XX
/8)
Watchdog timer 1 clock (f
XW
) Operation stops Operation starts
CPU Initialized Program execution starts after securing
oscillation stabilization time
Internal RAM
Undefined if power-on reset or writing data to RAM (by CPU) and reset input conflict
(data is damaged).
Otherwise value immediately before reset input is retained.
I/O lines (P00) Low-level output
I/O lines (ports other than P00) High impedance
On-chip peripheral I/O registers Initialized to specified status
Watchdog timer 2 Operation stops Operation starts (f
R
/8)
Other on-chip peripheral functions Operation stops Operation can be started after securing
oscillation stabilization time