CHAPTER 9 8-BIT TIMER H
User’s Manual U16896EJ2V0UD
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Figure 9-5. Operation Timing in PWM Output Mode (1/4)
Basic operation
Count clock
CMPn0
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
TOHn
(TOLEVn = 1)
00H 01H
A5H 00H 01H 02H
A5H 00H
A5H 00H
01H 02H
<1>
<3>
<2>
CMPn1
<4>
A5H
01H
8-bit timer counter
Hn count value
<1> When the TMHEn bit is set to 1, counting starts. At this time TOHn output remains the default level.
<2> When the count value of 8-bit timer counter Hn and the set value of the CMPn0 register match, the TOHn
output level is inverted, 8-bit timer counter Hn is cleared, and the INTTMHn signal is output.
<3> When the count value of 8-bit timer counter Hn and the set value of the CMPn1 register match, the TOHn
output level is inverted. At this time, the value of 8-bit timer counter Hn is not cleared and the INTTMHn
signal is not output.
<4> When the TMHEn bit is cleared to 0 during 8-bit timer Hn operation, the INTTMHn signal and TOHn
output are set to the default level.
Remark
n = 0, 1
