CHAPTER 21 CLOCK MONITOR
User’s Manual U16896EJ2V0UD
609
Figure 21-4. Reset Timing of Clock Monitor
Count operation or count stopped
f
X
f
CLK
f
R
CLMRES signal
(active low)
WDT2 count
CLME bit
CLMRF bit
Count operation continues
Stopped
Count operation
f
R
operation
Oscillation stabilization time secured
(count operation stops)
Main clock operation stopped
Watchdog timer 2 overflow
(WDTRES2 does not occur)
Watchdog timer 2 count operation starts
Main clock stop
detected
Program fetch
started
Remark
Software cannot be used to restore the normal operation mode from the internal oscillation clock
operation mode. After reset (generation of the RESET, WDTRES2, POCRES, or LVIRES signal), the
normal operation mode can be restored only if the main clock (f
X
) oscillates correctly.
