CHAPTER 13 A/D CONVERTER
User’s Manual U16896EJ2V0UD
380
(2) Scan
mode
In this mode, the analog signals specified by the ADS register and input from the ANI0 pin while the
ADM.ADMD bit = 1 are sequentially selected and converted.
When conversion of one analog input signal is complete, the conversion result is stored in the ADCR register
and, at the same time, the A/D conversion end interrupt request signal (INTAD) is generated.
The A/D conversion results of all the analog input signals are stored in the ADCR register. It is therefore
recommended to save the contents of the ADCR register to RAM once A/D conversion of one analog input
signal has been completed.
In the hardware trigger mode (ADS.TRG bit = 1), the A/D converter waits for a trigger after it has completed
A/D conversion of the analog signals specified by the ADS register and input from the ANI0 pin.
If anything is written to the ADM, ADS, PFM, and PFT registers during conversion in the high-speed mode
(ADHS1, ADHS0 bits = 01 or 10), A/D conversion is aborted. In the software trigger mode, A/D conversion is
started from the beginning again. In the hardware trigger mode, the A/D converter waits for a trigger.
Conversion starts again from the ANI0 pin. Inputting valid edge to the ADTRG pin is prohibited during A/D
conversion operation in the normal mode (ADHS1, ADHS0 bits = 00).
If the trigger is detected during conversion in hardware trigger mode in the high-speed mode (ADHS1, ADHS0
bits = 01 or 10), A/D conversion is aborted and started again from the beginning (ANI0 pin). Writing the ADM,
ADS, PFM, and PFT registers is prohibited during conversion operation in the normal mode (ADHS1, ADHS0
bits = 00).
<R>
<R>
