CHAPTER 21 CLOCK MONITOR
User’s Manual U16896EJ2V0UD
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21.5 Internal Oscillation HALT Mode
21.5.1 Setting and operation status
The internal oscillation HALT mode is set when a dedicated instruction (HALT instruction) is executed in the internal
oscillation clock operation mode.
In the internal oscillation HALT mode, the internal oscillator continues operating. Only clock supply to the CPU is
stopped; clock supply to the other on-chip peripheral functions continues.
As a result, program execution is stopped, and the internal RAM retains the contents before the internal oscillation
HALT mode was set. The on-chip peripheral functions that are independent of instruction processing by the CPU
continue operating. The main clock oscillator (f
X
) stops but the on-chip peripheral functions that can operate on the
subclock (f
XT
), internal oscillation clock (f
R
), or external clock continue operating.
Table 21-5 shows the operation status in the internal oscillation HALT mode.
Cautions 1. Insert five or more NOP instructions after the HALT instruction.
2. If the HALT instruction is executed with an unmasked interrupt request signal held pending,
the system shifts to the internal oscillation HALT mode, but the internal oscillation HALT
mode is immediately released by the pending interrupt request signal.
21.5.2 Releasing internal oscillation HALT mode
When the internal oscillation HALT mode is released by an interrupt request signal, the internal oscillation clock
operation mode is set. When the internal oscillation HALT mode is released by reset, the normal operation mode is
restored if the main clock (f
X
) oscillates correctly.
(1) Releasing internal oscillation HALT mode by non-maskable interrupt request signal or unmasked
maskable interrupt request signal
The internal oscillation HALT mode is released by a non-maskable interrupt request signal or an unmasked
maskable interrupt request signal, regardless of the priority of the interrupt request. If the internal oscillation
HALT mode is set in an interrupt servicing routine, however, an interrupt request that is issued later is serviced
as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, the internal oscillation HALT mode is released, but that interrupt request signal is not
acknowledged. The interrupt request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced
is issued (including a non-maskable interrupt request signal), the internal oscillation HALT mode is
released and that interrupt request signal is acknowledged.
Table 21-4. Operation After Releasing Internal Oscillation HALT Mode by Interrupt Request Signal
Release Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request signal
Execution branches to the handler address
Maskable interrupt request signal
Execution branches to the handler
address or the next instruction is
executed
The next instruction is executed
