CHAPTER 28 ELECTRICAL SPECIFICATIONS
User’s Manual U16896EJ2V0UD
666
Basic Operation
(1) Reset/external interrupt timing
(T
A
=
−
40 to +85
°
C, V
DD
= EV
DD
= AV
REF0
= 2.7 to 5.5 V, V
SS
= EV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
When digital noise
elimination not selected
2
μ
s
t
WRSL1
<87>
Reset in
power-on
status
When digital noise
elimination selected
Nr
×
t
RSMP
+ 2
μ
s
RESET low-level width
Note
t
WRSL2
<88>
Power-on
reset
3
ms
NMI high-level width
t
WNIH
<89> Analog noise elimination
1
μ
s
NMI low-level width
t
WNIL
<90> Analog noise elimination
1
μ
s
n = 0 to 7 (analog noise elimination)
600
ns
INTPn high-level width
t
WITH
<91>
n = 3 (when digital noise elimination selected)
Ni
×
t
ISMP
+ 200
ns
n = 0 to 7 (analog noise elimination)
600
ns
INTPn low-level width
t
WITL
<92>
n = 3 (when digital noise elimination selected)
Ni
×
t
ISMP
+ 200
ns
V
DD
= 4.0 to 5.5 V
T + 50
ns
ADTRG high-level width
t
WADH
<93>
V
DD
= 2.7 to 5.5 V
T + 100
ns
V
DD
= 4.0 to 5.5 V
T + 50
ns
ADTRG low-level width
t
WADL
<94>
V
DD
= 2.7 to 5.5 V
T + 100
ns
Note
The RESET low-level width is when the RESET pin input is valid (when POCRES is invalid).
Remarks 1.
Nr:
Number of samplings set by the RNZC.SMPSEL bit
t
RSMP
: Digital noise elimination sampling clock cycle of RESET pin
Ni:
Number of samplings set by the NFC.NFSTS bit
t
ISMP
: Digital noise elimination sampling clock cycle of INTP3 pin
T:
A/D base clock cycle (f
AD
)
2.
The above specification shows the pulse width that is accurately detected as a valid edge. If a pulse
narrower than the above specification is input, therefore, it may also be detected as a valid edge.
Reset/Interrupt
<88>
<87>
V
DD
RESET (input)
NMI (input)
INTPn (input)
ADTRG (input)
<89>/<91>/<93>
<90>/<92>/<94>
Remark
n = 0 to 7
<R>
<R>
