CHAPTER 5 CLOCK GENERATION FUNCTION
User’s Manual U16896EJ2V0UD
126
5.2 Configuration
Figure 5-1. Clock Generator
Internal
oscillator
INTBRG
CLKOUT
X1
X2
1/256
1/8
PLL
f
XX
/32
f
XX
/16
f
XX
/8
f
XX
/4
f
XX
/2
f
XX
f
CLK
f
XT
f
XX
f
X
f
R
/8
f
R
FRC bit
Subclock
oscillator
XT1
XT2
f
XT
Interval timer
BRG
f
BRG
= f
X
/2 to f
X
/2
12
IDLE mode
Watch timer clock
Watch timer clock,
watchdog timer 2 clock
CLS bit, CK3 bit
HALT
control
HALT mode
CPU clock
f
CPU
Peripheral clock
Watchdog timer 1 clock
Watchdog timer 2 clock
f
R
/2048
TMH1 clock
Internal
system clock
f
XX
to f
XX
/1024
f
XW
Selector
Selector
Selector
Selector
CK2 to CK0 bits
IDLE mode
IDLE mode
IDLE
control
IDLE
control
IDLE
control
Prescaler 2
Prescaler 1
Main clock stop
detection
MCK
bit
PLLON bit
SELPLL bit
STOP mode
Main clock
oscillator
Main clock
oscillator
stop control
MFRC
bit
Port CM
Remark
f
X
:
Main clock oscillation frequency
f
XX
: Main clock frequency
f
CLK
: Internal system clock frequency
f
XT
: Subclock
frequency
f
CPU
: CPU clock frequency
f
BRG
: Watch timer clock frequency
f
XW
: Watchdog timer 1 clock frequency
f
R
:
Internal oscillation clock frequency
<R>
