CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U16896EJ2V0UD
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(e) Generation timing of compare match interrupt request signal (INTTP0CC1)
The timing of generation of the INTTP0CC1 signal in the external trigger pulse output mode differs from
the timing of other INTTP0CC1 signals; the INTTP0CC1 signal is generated when the count value of the
16-bit counter matches the value of the TP0CCR1 register.
Count clock
16-bit counter
TP0CCR1 register
TOP01 pin output
INTTP0CC1 signal
D
1
D
1
−
2
D
1
−
1
D
1
D
1
+ 1
D
1
+ 2
Usually, the INTTP0CC1 signal is generated in synchronization with the next count up, after the count
value of the 16-bit counter matches the value of the TP0CCR1 register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the
timing is changed to match the timing of changing the output signal of the TOP01 pin.
