NEC V850ES/KE1+, User Manual

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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U16896EJ2V0UD
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17.8 Interrupt Response Time
Except in the following cases, the CPU interrupt response time is a minimum of 4 clocks. If inputting consecutive
interrupt request signals, at least 4 clocks must be placed between each interrupt request signal.
•
IDLE/STOP mode
•
External bus access
•
Consecutive interrupt request non-sample instruction (refer to 17.9 Periods in Which Interrupts Are Not
Acknowledged by CPU )
•
Access to interrupt control register
•
Access to peripheral I/O register
Figure 17-14. Pipeline Operation During Interrupt Request Signal Acknowledgment (Outline)
(1) Minimum interrupt response time
IF ID EX
Internal clock
Instruction 1
Instruction 2
Interrupt acknowledgment operation
Instruction (first instruction of interrupt servicing routine)
Interrupt request
IF ID EX MEM WB
IFX IDX
INT1 INT2 INT3 INT4
4 system clocks
(2) Maximum interrupt response time
IF ID EX
Internal clock
Instruction 1
Instruction 2
Interrupt acknowledgment operation
Instruction (first instruction of interrupt servicing routine)
Interrupt request
IF ID EX MEM MEM MEM WB
IFX IDX
INT1 INT2 INT3 INT3 INT3 INT4
6 system clocks
Remark INT1 to INT4: Interrupt acknowledgment processing
IFX: Invalid instruction fetch
IDX: Invalid instruction decode
Interrupt response time (internal system clock)
Internal interrupt External interrupt
Condition
Min. 4 4 + analog delay
Max. 6 6 + analog delay
The following cases are excluded.
•
IDLE/STOP mode
•
External bus access
•
Consecutive interrupt request non-sample instruction
•
Access to interrupt control register
•
Access to peripheral I/O register