CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
User’s Manual U16896EJ2V0UD
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6.7 Cautions
(1) Capture operation
When the capture operation is used and f
XX
/8, f
XX
/16, f
XX
/32, f
XX
/64, f
XX
/128, or the external event counter
(TP0CTL1.TP0EEE bit = 1) is selected as the count clock, FFFFH, not 0000H, may be captured in the
TP0CCRn register if the capture trigger is input immediately after the TP0CE bit is set to 1.
(a) Free-running timer mode
Count clock
0000H
FFFFH
TP0CE bit
TP0CCR0 register
FFFFH
0001H
0000H
TIP00 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX
)
Capture
trigger input
(b) Pulse width measurement mode
0000H
FFFFH
FFFFH
0002H
0000H
Count clock
TP0CE bit
TP0CCR0 register
TIP00 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX
)
Capture
trigger input