APPENDIX B INSTRUCTION SET LIST
User’s Manual U16896EJ2V0UD
699
Notes
12.
In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic
description and in the opcode differs from other instructions.
r r r r r
= regID specification
RRRRR = reg2 specification
13.
i i i i i : Lower 5 bits of imm9.
I I I I : Higher 4 bits of imm9.
14.
Do not specify the same register for general-purpose registers reg1 and reg3.
15.
sp/imm: specified by bits 19 and 20 of the sub-opcode.
16.
ff = 00: Load sp in ep.
01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
17.
If imm = imm32, n + 3 clocks.
18.
r r r r r : Other than 00000.
19.
ddddddd: Higher 7 bits of disp8.
20.
dddd: Higher 4 bits of disp5.
21.
dddddd: Higher 6 bits of disp8.
