CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User’s Manual U16896EJ2V0UD
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17.3 Maskable Interrupts
Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/KE1+ has 33
maskable interrupt sources (refer to
17.1.1 Features
).
If two or more maskable interrupt request signals are generated at the same time, they are acknowledged
according to the default priority. In addition to the default priority, eight levels of interrupt priorities can be specified by
using the interrupt control registers, allowing programmable priority control.
When an interrupt request signal has been acknowledged, the interrupt disabled (DI) status is set and the
acknowledgment of other maskable interrupt request signals is disabled.
When the EI instruction is executed in an interrupt servicing routine, the interrupt enabled (EI) status is set, which
enables acknowledgment of interrupt request signals having a priority higher than that of the interrupt request signal
currently in progress. Note that only interrupt request signals with a higher priority have this capability; interrupt
request signals with the same priority level cannot be nested.
To use multiple interrupts, it is necessary to save EIPC and EIPSW to memory or a register before executing the EI
instruction, and restore EIPC and EIPSW to the original values by executing the DI instruction before the RETI
instruction.
When the WDTM1.WDTM14 bit is cleared to 0, the watchdog timer 1 overflow interrupt functions as a maskable
interrupt (INTWDTM1).
17.3.1 Operation
If a maskable interrupt request signal is generated, the CPU performs the following processing and transfers
control to a handler routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the PSW.ID bit to 1 and clears the PSW.EP bit to 0.
<5> Loads the corresponding handler address to the PC and transfers control.
The maskable interrupt request signal masked by INTC and the maskable interrupt request signal that occurs while
another interrupt is being serviced (when PSW.NP bit = 1 or ID bit = 1) are held pending internally. When the
interrupts are unmasked, or when the NP bit = 0 and the ID bit = 0 by using the RETI and LDSR instructions, a new
maskable interrupt servicing is started in accordance with the priority of the pending maskable interrupt request signal.
Figure 17-4 shows the servicing flow for maskable interrupts.
