CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5
User’s Manual U16896EJ2V0UD
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8.4 Operation
8.4.1 Operation as interval timer
8-bit timer/event counter 5n operates as an interval timer that repeatedly generates interrupts at the interval of the
count value preset in the CR5n register. If the count value in the TM5n register matches the value set in the CR5n
register, the value of the TM5n register is cleared to 00H and counting is continued, and at the same time, an interrupt
request signal (INTTM5n) is generated.
Setting method
<1> Set each register.
•
TCL5n register: Selects the count clock (t).
•
CR5n register:
Compare value (N)
•
TMC5n register: Stops count operation and selects the mode in which clear & start occurs on a match
between the TM5n register and CR5n register (TMC5n register = 0000xx00B,
×
: don’t care).
<2> When the TMC5n.TCE5n bit is set to 1, the count operation starts.
<3> When the values of the TM5n register and CR5n register match, the INTTM5n signal is generated (TM5n
register is cleared to 00H).
<4> Then, the INTTM5n signal is repeatedly generated at the same interval. To stop counting, set the TCE5n
bit = 0.
Interval time = (N + 1)
×
t: N = 00H to FFH
Caution During interval timer operation, do not rewrite the value of the CR5n register.
Remark
n = 0, 1
Figure 8-2. Timing of Interval Timer Operation (1/2)
Basic operation
t
Interval time
Interval time
00H
N
01H
01H
00H
N
N
N
N
N
N
01H
00H
Clear
Interrupt acknowledgment Interrupt acknowledgment
Clear
Count clock
TM5n count value
CR5n
TCE5n
INTTM5n
Count start
Remark
n = 0, 1
