CHAPTER 9 8-BIT TIMER H
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9.4.2 PWM output mode operation
In the PWM output mode, a pulse of any duty and cycle can be output.
The CMPn0 register controls the timer output (TOHn) cycle. Rewriting the CMPn0 register during timer operation
is prohibited.
The CMPn1 register controls the timer output (TOHn) duty. The CMPn1 register can be rewritten during timer
operation.
The operation in the PWM output mode is as follows.
After timer counting starts, when the count value of 8-bit timer counter Hn and the set value of the CMPn0 register
match, the TOHn output level is inverted and 8-bit timer counter Hn is cleared to 00H. When the count value of 8-bit
timer counter Hn and the set value of the CMPn1 register match, the TOHn output level is inverted.
Remarks 1.
For the alternate-function pin (TOHn) settings, refer to
Table 4-12 Settings When Port Pins Are
Used for Alternate Functions
.
2.
For INTTMHn interrupt enable, refer to
CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING
FUNCTION
.
Setting
<1> Set each register.
Figure 9-4. Register Settings in PWM Output Mode
(i) 8-bit timer H mode register n (TMHMDn) settings
0
0/1
0/1
0/1
1
Enables timer output
Sets timer output default level
Selects PWM output mode
Selects count clock (f
CNT
)
Stops count operation
0
0/1
1
TMMDn0 TOLEVn
TOENn
CKSHn1
CKSHn2
TMHEn
TMHMDn
CKSHn0 TMMDn1
(ii) CMPn0 register setting
•
Compare value (N): Sets cycle
(iii) CMPn1 register setting
•
Compare value (M): Sets duty
Remarks 1.
n = 0, 1
2.
00H
≤
CMPn1 (M) < CMPn0 (N)
≤
FFH
<2> When the TMHEn bit is set to 1, counting starts.
